[llvm] [AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR (PR #170335)

[Matt Arsenault via llvm-commits]

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@@ -1837,6 +1945,532 @@ void GCNSchedStage::revertScheduling() {
   DAG.Regions[RegionIdx] = std::pair(DAG.RegionBegin, DAG.RegionEnd);
 }
 
+bool RewriteScheduleStage::isRewriteCandidate(MachineInstr *MI) const {
+
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arsenm wrote:

Duplicating the core rewrite logic from AMDGPURewriteAGPRCopyMFMA is unfortunate. This should eventually cover more cases, like https://github.com/llvm/llvm-project/issues/168983

https://github.com/llvm/llvm-project/pull/170335