[llvm] [Doc][AMDGPU] Add barrier execution & memory model (PR #170447)

[Nicolai Hähnle via llvm-commits]

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@@ -6797,6 +7110,10 @@ only accessed by a single thread, and is always write-before-read, there is
 never a need to invalidate these entries from the L1 cache. Hence all cache
 invalidates are done as ``*_vol`` to only invalidate the volatile cache lines.
 
+A wave waiting on a ``s_barrier`` is unable to handle traps or exceptions,
+thus a ``s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)`` is required before entering
+the barrier so that no memory exception can occur during the barrier.
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nhaehnle wrote:

Don't some of these parts wait for those counters implicitly? It's been a long time...

https://github.com/llvm/llvm-project/pull/170447