[llvm] [AMDGPU] Add verifier for flat_scr_base_hi read hazard (PR #170550)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -5808,6 +5808,17 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
     }
   }
 
+  if (ST.hasFlatScratchHiInB64InstHazard() && isSALU(MI) &&
+      MI.readsRegister(AMDGPU::SRC_FLAT_SCRATCH_BASE_HI, nullptr)) {
+    const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::sdst);
+    if ((Dst && AMDGPU::getRegBitWidth(
+                    *RI.getRegClassForReg(MRI, Dst->getReg())) == 64) ||
+        Opcode == AMDGPU::S_BITCMP0_B64 || Opcode == AMDGPU::S_BITCMP1_B64) {
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rampitec wrote:

These do not have `sdst` but listed as hazard in the ticket.

https://github.com/llvm/llvm-project/pull/170550