[llvm] [docs] [RISCV] Update docs regarding RV32E/RV64E (PR #170707)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Robin Kastberg (RobinKastberg)

<details>
<summary>Changes</summary>

Since #<!-- -->76777 RV32E and RV64E has been fully supported, 
but this guide was not updated.

---
Full diff: https://github.com/llvm/llvm-project/pull/170707.diff


1 Files Affected:

- (modified) llvm/docs/RISCVUsage.rst (+1-2) 


``````````diff
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 49184e3104868..513b2015edd22 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -53,8 +53,7 @@ Base ISAs
 =========
 
 The specification defines five base instruction sets: RV32I, RV32E, RV64I,
-RV64E, and RV128I. Currently, LLVM fully supports RV32I, and RV64I.  RV32E and
-RV64E are supported by the assembly-based tools only.  RV128I is not supported.
+RV64E, and RV128I. Currently, RV128I is not supported.
 
 To specify the target triple:
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/170707