[llvm] [docs] [RISCV] Update docs regarding RV32E/RV64E (PR #170707)

[Robin Kastberg via llvm-commits]

https://github.com/RobinKastberg created https://github.com/llvm/llvm-project/pull/170707

Since #76777 RV32E and RV64E has been fully supported, 
but this guide was not updated.

>From be50993ff119623fe9b32ab2c2090e7669bb2f41 Mon Sep 17 00:00:00 2001
From: Robin Kastberg <robin.kastberg at iar.com>
Date: Thu, 4 Dec 2025 18:44:24 +0100
Subject: [PATCH] [docs] [RISCV] Update docs regarding RV32E/RV64E

Since #76777 RV32E and RV64E has been fully supported, but
this guide was not updated.

Signed-off-by: Robin Kastberg <robin.kastberg at iar.com>
---
 llvm/docs/RISCVUsage.rst | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 49184e3104868..513b2015edd22 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -53,8 +53,7 @@ Base ISAs
 =========
 
 The specification defines five base instruction sets: RV32I, RV32E, RV64I,
-RV64E, and RV128I. Currently, LLVM fully supports RV32I, and RV64I.  RV32E and
-RV64E are supported by the assembly-based tools only.  RV128I is not supported.
+RV64E, and RV128I. Currently, RV128I is not supported.
 
 To specify the target triple: