[llvm] [RISCV][llvm] Support VFADD, VFSUB, VFMUL codegen for Zvfbfa (PR #170612)

[Craig Topper via llvm-commits]

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@@ -215,8 +215,8 @@ multiclass VPatBinaryFPSDNode_VV_VF<SDPatternOperator vop, string instruction_na
 }
 
 multiclass VPatBinaryFPSDNode_VV_VF_RM<SDPatternOperator vop, string instruction_name,
-                                       bit isSEWAware = 0> {
-  foreach vti = AllFloatVectors in {
+                                       bit isSEWAware = 0, bit isBF16 = 0> {
+  foreach vti = !if(isBF16, AllBF16Vectors, AllFloatVectors) in {
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topperc wrote:

If you used a single instantiation, the isBF16 argument wouldn't exist. So you'd have to get it from `fvti`.

https://github.com/llvm/llvm-project/pull/170612