[llvm] [RISCV] Use vsetivli instead of `x0,x0` form to retain SEW/LMUL when AVL is imm (PR #169307)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 3 23:27:33 PST 2025

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https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/169307

Previous message: [llvm] [RISCV] Use vsetivli instead of `x0,x0` form to retain SEW/LMUL when AVL is imm (PR #169307)
Next message: [llvm] [RISCV] Update P extension to the 018 version of the spec. (PR #170399)
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