[llvm] cb5ccab - [RISCV][NFC] Simplify Imm range checks (#170497)
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llvm-commits at lists.llvm.org
Wed Dec 3 21:04:53 PST 2025
Author: Piotr Fusik
Date: 2025-12-04T06:04:49+01:00
New Revision: cb5ccabbad0b2627dc9355e707233be136236d45
URL: https://github.com/llvm/llvm-project/commit/cb5ccabbad0b2627dc9355e707233be136236d45
DIFF: https://github.com/llvm/llvm-project/commit/cb5ccabbad0b2627dc9355e707233be136236d45.diff
LOG: [RISCV][NFC] Simplify Imm range checks (#170497)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVGISel.td
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index eba35ef0a746d..67d2cacd5cdb9 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -17,14 +17,14 @@ include "RISCV.td"
include "RISCVCombine.td"
def simm12Plus1 : ImmLeaf<XLenVT, [{
- return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
+ return Imm >= -2047 && Imm <= 2048;}]>;
def simm12Plus1i32 : ImmLeaf<i32, [{
- return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
+ return Imm >= -2047 && Imm <= 2048;}]>;
// FIXME: This doesn't check that the G_CONSTANT we're deriving the immediate
// from is only used once
def simm12Minus1Nonzero : ImmLeaf<XLenVT, [{
- return (Imm >= -2049 && Imm < 0) || (Imm > 0 && Imm <= 2046);}]>;
+ return Imm >= -2049 && Imm <= 2046 && Imm != 0;}]>;
def simm12Minus1NonzeroNonNeg1 : ImmLeaf<XLenVT, [{
return (Imm >= -2049 && Imm < -1) || (Imm > 0 && Imm <= 2046);}]>;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 7cf6f203fda89..b92926e63d880 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -4315,14 +4315,14 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
- [](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
+ [](int64_t Imm) { return Imm >= -15 && Imm <= 16; },
/*Decrement=*/true);
}
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
- [](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
+ [](int64_t Imm) { return Imm >= -15 && Imm <= 16; },
/*Decrement=*/false);
}
@@ -4330,9 +4330,7 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
- [](int64_t Imm) {
- return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
- },
+ [](int64_t Imm) { return Imm != 0 && Imm >= -15 && Imm <= 16; },
/*Decrement=*/true);
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 89ec4a2a4a3e1..2bd63e75d060b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2904,7 +2904,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isUInt<5>(Imm) && (Imm > 3);
break;
case RISCVOp::OPERAND_UIMM5_PLUS1:
- Ok = (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
+ Ok = Imm >= 1 && Imm <= 32;
break;
case RISCVOp::OPERAND_UIMM6_LSB0:
Ok = isShiftedUInt<5, 1>(Imm);
@@ -2957,7 +2957,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
CASE_OPERAND_SIMM(26)
// clang-format on
case RISCVOp::OPERAND_SIMM5_PLUS1:
- Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
+ Ok = Imm >= -15 && Imm <= 16;
break;
case RISCVOp::OPERAND_SIMM5_NONZERO:
Ok = isInt<5>(Imm) && (Imm != 0);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 84b962b2a8607..a27c46ebf3a99 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -507,7 +507,7 @@ def ixlenimm_li_restricted : Operand<XLenVT> {
// A 12-bit signed immediate plus one where the imm range will be -2047~2048.
def simm12_plus1 : ImmLeaf<XLenVT,
- [{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
+ [{return Imm >= -2047 && Imm <= 2048;}]>;
// A 6-bit constant greater than 32.
def uimm6gt32 : ImmLeaf<XLenVT, [{
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index f46455a9acedf..594a75a4746d4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -79,19 +79,19 @@ def simm5 : RISCVSImmLeafOp<5> {
}
def simm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
- [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
+ [{return Imm >= -15 && Imm <= 16;}]> {
let ParserMatchClass = SImmAsmOperand<5, "Plus1">;
let OperandType = "OPERAND_SIMM5_PLUS1";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
- return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
+ return Imm >= -15 && Imm <= 16;
return MCOp.isBareSymbolRef();
}];
}
def simm5_plus1_nonzero : ImmLeaf<XLenVT,
- [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
+ [{return Imm != 0 && Imm >= -15 && Imm <= 16;}]>;
//===----------------------------------------------------------------------===//
// Scheduling definitions.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 13ceead2d28b4..748494ffc2935 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -62,7 +62,7 @@ def UImm5Plus1AsmOperand : AsmOperandClass {
}
def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
- [{return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);}]> {
+ [{return Imm >= 1 && Imm <= 32;}]> {
let ParserMatchClass = UImm5Plus1AsmOperand;
let EncoderMethod = "getImmOpValueMinus1";
let DecoderMethod = "decodeUImmPlus1Operand<5>";
@@ -71,12 +71,12 @@ def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
+ return Imm >= 1 && Imm <= 32;
}];
}
def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
- [{return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));}]> {
+ [{return Imm >= 6 && Imm <= 32;}]> {
let ParserMatchClass = UImmAsmOperand<5, "GE6Plus1">;
let EncoderMethod = "getImmOpValueMinus1";
let DecoderMethod = "decodeUImmPlus1OperandGE<5,6>";
@@ -85,7 +85,7 @@ def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));
+ return Imm >= 6 && Imm <= 32;
}];
}
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