[llvm] [RISCV][NFC] Simplify Imm range checks (PR #170497)
Piotr Fusik via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 3 11:18:31 PST 2025
https://github.com/pfusik updated https://github.com/llvm/llvm-project/pull/170497
>From e71c755a9b399c6d0fae10d66a9006d751cc4aab Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Wed, 3 Dec 2025 16:38:17 +0100
Subject: [PATCH 1/3] [RISCV][NFC] Simplify Imm range checks
---
llvm/lib/Target/RISCV/RISCVGISel.td | 6 +++---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 6 +++---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 14 +++++++-------
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 4 ++--
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 19 +++++++++----------
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 6 +++---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 20 ++++++++++----------
llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td | 2 +-
8 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index eba35ef0a746d..67d2cacd5cdb9 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -17,14 +17,14 @@ include "RISCV.td"
include "RISCVCombine.td"
def simm12Plus1 : ImmLeaf<XLenVT, [{
- return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
+ return Imm >= -2047 && Imm <= 2048;}]>;
def simm12Plus1i32 : ImmLeaf<i32, [{
- return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
+ return Imm >= -2047 && Imm <= 2048;}]>;
// FIXME: This doesn't check that the G_CONSTANT we're deriving the immediate
// from is only used once
def simm12Minus1Nonzero : ImmLeaf<XLenVT, [{
- return (Imm >= -2049 && Imm < 0) || (Imm > 0 && Imm <= 2046);}]>;
+ return Imm >= -2049 && Imm <= 2046 && Imm != 0;}]>;
def simm12Minus1NonzeroNonNeg1 : ImmLeaf<XLenVT, [{
return (Imm >= -2049 && Imm < -1) || (Imm > 0 && Imm <= 2046);}]>;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 7cf6f203fda89..88431ed1c7ad1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -4315,14 +4315,14 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
- [](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
+ [](int64_t Imm) { return Imm >= -15 && Imm <= 16; },
/*Decrement=*/true);
}
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
- [](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
+ [](int64_t Imm) { return Imm >= -15 && Imm <= 16; },
/*Decrement=*/false);
}
@@ -4331,7 +4331,7 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) {
- return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
+ return Imm != 0 && Imm >= -15 && Imm <= 16;
},
/*Decrement=*/true);
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 89ec4a2a4a3e1..037786c32ebbe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2898,13 +2898,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isShiftedUInt<4, 1>(Imm);
break;
case RISCVOp::OPERAND_UIMM5_NONZERO:
- Ok = isUInt<5>(Imm) && (Imm != 0);
+ Ok = Imm >= 1 && Imm <= 31;
break;
case RISCVOp::OPERAND_UIMM5_GT3:
- Ok = isUInt<5>(Imm) && (Imm > 3);
+ Ok = Imm >= 4 && Imm <= 31;
break;
case RISCVOp::OPERAND_UIMM5_PLUS1:
- Ok = (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
+ Ok = Imm >= 1 && Imm <= 32;
break;
case RISCVOp::OPERAND_UIMM6_LSB0:
Ok = isShiftedUInt<5, 1>(Imm);
@@ -2937,7 +2937,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_UIMM16_NONZERO:
- Ok = isUInt<16>(Imm) && (Imm != 0);
+ Ok = Imm >= 1 && Imm <= 65535;
break;
case RISCVOp::OPERAND_THREE:
Ok = Imm == 3;
@@ -2946,7 +2946,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = Imm == 4;
break;
case RISCVOp::OPERAND_IMM5_ZIBI:
- Ok = (isUInt<5>(Imm) && Imm != 0) || Imm == -1;
+ Ok = (Imm >= 1 && Imm <= 31) || Imm == -1;
break;
// clang-format off
CASE_OPERAND_SIMM(5)
@@ -2957,7 +2957,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
CASE_OPERAND_SIMM(26)
// clang-format on
case RISCVOp::OPERAND_SIMM5_PLUS1:
- Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
+ Ok = Imm >= -15 && Imm <= 16;
break;
case RISCVOp::OPERAND_SIMM5_NONZERO:
Ok = isInt<5>(Imm) && (Imm != 0);
@@ -2991,7 +2991,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = Ok && Imm != 0;
break;
case RISCVOp::OPERAND_CLUI_IMM:
- Ok = (isUInt<5>(Imm) && Imm != 0) ||
+ Ok = (Imm >= 1 && Imm <= 31) ||
(Imm >= 0xfffe0 && Imm <= 0xfffff);
break;
case RISCVOp::OPERAND_RVKRNUM:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 84b962b2a8607..99dda07b582f9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -507,11 +507,11 @@ def ixlenimm_li_restricted : Operand<XLenVT> {
// A 12-bit signed immediate plus one where the imm range will be -2047~2048.
def simm12_plus1 : ImmLeaf<XLenVT,
- [{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
+ [{return Imm >= -2047 && Imm <= 2048;}]>;
// A 6-bit constant greater than 32.
def uimm6gt32 : ImmLeaf<XLenVT, [{
- return isUInt<6>(Imm) && Imm > 32;
+ return Imm >= 33 && Imm <= 63;
}]>;
// Addressing modes.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 24e7a0ee5a79f..f30d2a772bdd4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -17,9 +17,7 @@ def UImmLog2XLenNonZeroAsmOperand : AsmOperandClass {
}
def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{
- if (Subtarget->is64Bit())
- return isUInt<6>(Imm) && (Imm != 0);
- return isUInt<5>(Imm) && (Imm != 0);
+ return Imm >= 1 && Imm <= (Subtarget->is64Bit() ? 63 : 31);
}]> {
let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;
let DecoderMethod = "decodeUImmLog2XLenNonZeroOperand";
@@ -28,9 +26,11 @@ def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
+ if (Imm <= 0)
+ return false;
if (STI.getTargetTriple().isArch64Bit())
- return isUInt<6>(Imm) && (Imm != 0);
- return isUInt<5>(Imm) && (Imm != 0);
+ return Imm <= 63;
+ return Imm <= 31;
}];
}
@@ -70,9 +70,8 @@ def CLUIImmAsmOperand : AsmOperandClass {
// bit 17. Therefore, this 6-bit immediate can represent values in the ranges
// [1, 31] and [0xfffe0, 0xfffff].
def c_lui_imm : RISCVOp,
- ImmLeaf<XLenVT, [{return (Imm != 0) &&
- (isUInt<5>(Imm) ||
- (Imm >= 0xfffe0 && Imm <= 0xfffff));}]> {
+ ImmLeaf<XLenVT, [{return (Imm >= 1 && Imm <= 31) ||
+ (Imm >= 0xfffe0 && Imm <= 0xfffff);}]> {
let ParserMatchClass = CLUIImmAsmOperand;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeCLUIImmOperand";
@@ -81,8 +80,8 @@ def c_lui_imm : RISCVOp,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return (Imm != 0) && (isUInt<5>(Imm) ||
- (Imm >= 0xfffe0 && Imm <= 0xfffff));
+ return (Imm >= 1 && Imm <= 31) ||
+ (Imm >= 0xfffe0 && Imm <= 0xfffff);
}];
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index f46455a9acedf..594a75a4746d4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -79,19 +79,19 @@ def simm5 : RISCVSImmLeafOp<5> {
}
def simm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
- [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
+ [{return Imm >= -15 && Imm <= 16;}]> {
let ParserMatchClass = SImmAsmOperand<5, "Plus1">;
let OperandType = "OPERAND_SIMM5_PLUS1";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
- return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
+ return Imm >= -15 && Imm <= 16;
return MCOp.isBareSymbolRef();
}];
}
def simm5_plus1_nonzero : ImmLeaf<XLenVT,
- [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
+ [{return Imm != 0 && Imm >= -15 && Imm <= 16;}]>;
//===----------------------------------------------------------------------===//
// Scheduling definitions.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 13ceead2d28b4..3508224c60d7d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -32,7 +32,7 @@ def qc_insb : RVSDNode<"QC_INSB", SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
def qc_e_li : RVSDNode<"QC_E_LI", SDTIntUnaryOp>;
def uimm5nonzero : RISCVOp<XLenVT>,
- ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]> {
+ ImmLeaf<XLenVT, [{return Imm >= 1 && Imm <= 31;}]> {
let ParserMatchClass = UImmAsmOperand<5, "NonZero">;
let DecoderMethod = "decodeUImmNonZeroOperand<5>";
let OperandType = "OPERAND_UIMM5_NONZERO";
@@ -40,20 +40,20 @@ def uimm5nonzero : RISCVOp<XLenVT>,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return (Imm != 0) && isUInt<5>(Imm);;
+ return Imm >= 1 && Imm <= 31;
}];
}
-def tuimm5nonzero : TImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]>;
+def tuimm5nonzero : TImmLeaf<XLenVT, [{return Imm >= 1 && Imm <= 31;}]>;
def uimm5gt3 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
- [{return (Imm > 3) && isUInt<5>(Imm);}]> {
+ [{return Imm >= 4 && Imm <= 31;}]> {
let ParserMatchClass = UImmAsmOperand<5, "GT3">;
let DecoderMethod = "decodeUImmOperandGE<5, 4>";
let OperandType = "OPERAND_UIMM5_GT3";
}
-def tuimm5gt3 : TImmLeaf<XLenVT, [{return (Imm > 3) && isUInt<5>(Imm);}]>;
+def tuimm5gt3 : TImmLeaf<XLenVT, [{return Imm >= 4 && Imm <= 31;}]>;
def UImm5Plus1AsmOperand : AsmOperandClass {
let Name = "UImm5Plus1";
@@ -62,7 +62,7 @@ def UImm5Plus1AsmOperand : AsmOperandClass {
}
def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
- [{return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);}]> {
+ [{return Imm >= 1 && Imm <= 32;}]> {
let ParserMatchClass = UImm5Plus1AsmOperand;
let EncoderMethod = "getImmOpValueMinus1";
let DecoderMethod = "decodeUImmPlus1Operand<5>";
@@ -71,12 +71,12 @@ def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
+ return Imm >= 1 && Imm <= 32;
}];
}
def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
- [{return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));}]> {
+ [{return Imm >= 6 && Imm <= 32;}]> {
let ParserMatchClass = UImmAsmOperand<5, "GE6Plus1">;
let EncoderMethod = "getImmOpValueMinus1";
let DecoderMethod = "decodeUImmPlus1OperandGE<5,6>";
@@ -85,7 +85,7 @@ def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));
+ return Imm >= 6 && Imm <= 32;
}];
}
@@ -129,7 +129,7 @@ def uimm14lsb00 : RISCVOp,
}
def uimm16nonzero : RISCVOp<XLenVT>,
- ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<16>(Imm);}]> {
+ ImmLeaf<XLenVT, [{return Imm >= 1 && Imm <= 65535;}]> {
let ParserMatchClass = UImmAsmOperand<16, "NonZero">;
let DecoderMethod = "decodeUImmNonZeroOperand<16>";
let OperandType = "OPERAND_UIMM16_NONZERO";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
index 412bb08b00929..5caae543bf6ba 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
@@ -12,7 +12,7 @@
// A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1.
def imm5_zibi : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{
- return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1;
+ return Imm != 0 && Imm >= -1 && Imm <= 31;
}]> {
let ParserMatchClass = ImmAsmOperand<"", 5, "Zibi">;
let EncoderMethod = "getImmOpValueZibi";
>From ca1d13a9c101fbb76344725adf9e0e53edd821b6 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Wed, 3 Dec 2025 16:43:26 +0100
Subject: [PATCH 2/3] [RISCV][NFC] clang-format
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 4 +---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 3 +--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 88431ed1c7ad1..b92926e63d880 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -4330,9 +4330,7 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
- [](int64_t Imm) {
- return Imm != 0 && Imm >= -15 && Imm <= 16;
- },
+ [](int64_t Imm) { return Imm != 0 && Imm >= -15 && Imm <= 16; },
/*Decrement=*/true);
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 037786c32ebbe..1364b9f260ff9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2991,8 +2991,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = Ok && Imm != 0;
break;
case RISCVOp::OPERAND_CLUI_IMM:
- Ok = (Imm >= 1 && Imm <= 31) ||
- (Imm >= 0xfffe0 && Imm <= 0xfffff);
+ Ok = (Imm >= 1 && Imm <= 31) || (Imm >= 0xfffe0 && Imm <= 0xfffff);
break;
case RISCVOp::OPERAND_RVKRNUM:
Ok = Imm >= 0 && Imm <= 10;
>From eb3b594410965731165a58d2150ff954e9171977 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Wed, 3 Dec 2025 20:09:02 +0100
Subject: [PATCH 3/3] [RISCV][NFC] Revert `isUInt<N>(Imm) && lowerBoundCond`
checks
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 11 ++++++-----
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 19 ++++++++++---------
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 12 ++++++------
llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td | 2 +-
5 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 1364b9f260ff9..2bd63e75d060b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2898,10 +2898,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isShiftedUInt<4, 1>(Imm);
break;
case RISCVOp::OPERAND_UIMM5_NONZERO:
- Ok = Imm >= 1 && Imm <= 31;
+ Ok = isUInt<5>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_UIMM5_GT3:
- Ok = Imm >= 4 && Imm <= 31;
+ Ok = isUInt<5>(Imm) && (Imm > 3);
break;
case RISCVOp::OPERAND_UIMM5_PLUS1:
Ok = Imm >= 1 && Imm <= 32;
@@ -2937,7 +2937,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_UIMM16_NONZERO:
- Ok = Imm >= 1 && Imm <= 65535;
+ Ok = isUInt<16>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_THREE:
Ok = Imm == 3;
@@ -2946,7 +2946,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = Imm == 4;
break;
case RISCVOp::OPERAND_IMM5_ZIBI:
- Ok = (Imm >= 1 && Imm <= 31) || Imm == -1;
+ Ok = (isUInt<5>(Imm) && Imm != 0) || Imm == -1;
break;
// clang-format off
CASE_OPERAND_SIMM(5)
@@ -2991,7 +2991,8 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = Ok && Imm != 0;
break;
case RISCVOp::OPERAND_CLUI_IMM:
- Ok = (Imm >= 1 && Imm <= 31) || (Imm >= 0xfffe0 && Imm <= 0xfffff);
+ Ok = (isUInt<5>(Imm) && Imm != 0) ||
+ (Imm >= 0xfffe0 && Imm <= 0xfffff);
break;
case RISCVOp::OPERAND_RVKRNUM:
Ok = Imm >= 0 && Imm <= 10;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 99dda07b582f9..a27c46ebf3a99 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -511,7 +511,7 @@ def simm12_plus1 : ImmLeaf<XLenVT,
// A 6-bit constant greater than 32.
def uimm6gt32 : ImmLeaf<XLenVT, [{
- return Imm >= 33 && Imm <= 63;
+ return isUInt<6>(Imm) && Imm > 32;
}]>;
// Addressing modes.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index f30d2a772bdd4..24e7a0ee5a79f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -17,7 +17,9 @@ def UImmLog2XLenNonZeroAsmOperand : AsmOperandClass {
}
def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{
- return Imm >= 1 && Imm <= (Subtarget->is64Bit() ? 63 : 31);
+ if (Subtarget->is64Bit())
+ return isUInt<6>(Imm) && (Imm != 0);
+ return isUInt<5>(Imm) && (Imm != 0);
}]> {
let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;
let DecoderMethod = "decodeUImmLog2XLenNonZeroOperand";
@@ -26,11 +28,9 @@ def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- if (Imm <= 0)
- return false;
if (STI.getTargetTriple().isArch64Bit())
- return Imm <= 63;
- return Imm <= 31;
+ return isUInt<6>(Imm) && (Imm != 0);
+ return isUInt<5>(Imm) && (Imm != 0);
}];
}
@@ -70,8 +70,9 @@ def CLUIImmAsmOperand : AsmOperandClass {
// bit 17. Therefore, this 6-bit immediate can represent values in the ranges
// [1, 31] and [0xfffe0, 0xfffff].
def c_lui_imm : RISCVOp,
- ImmLeaf<XLenVT, [{return (Imm >= 1 && Imm <= 31) ||
- (Imm >= 0xfffe0 && Imm <= 0xfffff);}]> {
+ ImmLeaf<XLenVT, [{return (Imm != 0) &&
+ (isUInt<5>(Imm) ||
+ (Imm >= 0xfffe0 && Imm <= 0xfffff));}]> {
let ParserMatchClass = CLUIImmAsmOperand;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeCLUIImmOperand";
@@ -80,8 +81,8 @@ def c_lui_imm : RISCVOp,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return (Imm >= 1 && Imm <= 31) ||
- (Imm >= 0xfffe0 && Imm <= 0xfffff);
+ return (Imm != 0) && (isUInt<5>(Imm) ||
+ (Imm >= 0xfffe0 && Imm <= 0xfffff));
}];
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 3508224c60d7d..748494ffc2935 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -32,7 +32,7 @@ def qc_insb : RVSDNode<"QC_INSB", SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
def qc_e_li : RVSDNode<"QC_E_LI", SDTIntUnaryOp>;
def uimm5nonzero : RISCVOp<XLenVT>,
- ImmLeaf<XLenVT, [{return Imm >= 1 && Imm <= 31;}]> {
+ ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<5, "NonZero">;
let DecoderMethod = "decodeUImmNonZeroOperand<5>";
let OperandType = "OPERAND_UIMM5_NONZERO";
@@ -40,20 +40,20 @@ def uimm5nonzero : RISCVOp<XLenVT>,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return Imm >= 1 && Imm <= 31;
+ return (Imm != 0) && isUInt<5>(Imm);;
}];
}
-def tuimm5nonzero : TImmLeaf<XLenVT, [{return Imm >= 1 && Imm <= 31;}]>;
+def tuimm5nonzero : TImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]>;
def uimm5gt3 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
- [{return Imm >= 4 && Imm <= 31;}]> {
+ [{return (Imm > 3) && isUInt<5>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<5, "GT3">;
let DecoderMethod = "decodeUImmOperandGE<5, 4>";
let OperandType = "OPERAND_UIMM5_GT3";
}
-def tuimm5gt3 : TImmLeaf<XLenVT, [{return Imm >= 4 && Imm <= 31;}]>;
+def tuimm5gt3 : TImmLeaf<XLenVT, [{return (Imm > 3) && isUInt<5>(Imm);}]>;
def UImm5Plus1AsmOperand : AsmOperandClass {
let Name = "UImm5Plus1";
@@ -129,7 +129,7 @@ def uimm14lsb00 : RISCVOp,
}
def uimm16nonzero : RISCVOp<XLenVT>,
- ImmLeaf<XLenVT, [{return Imm >= 1 && Imm <= 65535;}]> {
+ ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<16>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<16, "NonZero">;
let DecoderMethod = "decodeUImmNonZeroOperand<16>";
let OperandType = "OPERAND_UIMM16_NONZERO";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
index 5caae543bf6ba..412bb08b00929 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
@@ -12,7 +12,7 @@
// A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1.
def imm5_zibi : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{
- return Imm != 0 && Imm >= -1 && Imm <= 31;
+ return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1;
}]> {
let ParserMatchClass = ImmAsmOperand<"", 5, "Zibi">;
let EncoderMethod = "getImmOpValueZibi";
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