[llvm] [Exegesis][RISCV] Support C_LDSP for llvm-exegesis (PR #169660)

[Min-Yih Hsu via llvm-commits]

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@@ -819,6 +819,15 @@ void ExegesisRISCVTarget::fillMemoryOperands(InstructionTemplate &IT,
 
   assert(MemOp.isReg() && "Memory operand expected to be register");
 
+  unsigned Opcode = I.getOpcode();
+  if (Opcode == RISCV::C_LDSP || Opcode == RISCV::C_LWSP ||
+      Opcode == RISCV::C_SDSP || Opcode == RISCV::C_SWSP) {
+    // Force base register to SP (X2)
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mshockwave wrote:

nit: this comment should be applied to the _next_ line (i.e. line 827): `I.Operands[0]` is the `rd` not base register

https://github.com/llvm/llvm-project/pull/169660