[llvm] [RISCV] Clear kill flags for FalseReg in foldVMergeToMask (PR #170438)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)

<details>
<summary>Changes</summary>

Or we can't pass the MachineVerifier because of using a killed virtual
register.

This was found when backporting #<!-- -->170070 to 21.x branch.



---
Full diff: https://github.com/llvm/llvm-project/pull/170438.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp (+2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir (+51) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 5acb7f5bcd56a..66001ff8cbd03 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -834,6 +834,8 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
     MRI->constrainRegClass(
         MO.getReg(), True.getRegClassConstraint(MO.getOperandNo(), TII, TRI));
   }
+  // We should clear the IsKill flag since we have an use now.
+  MRI->clearKillFlags(FalseReg);
   MI.eraseFromParent();
 
   return true;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
index 338732c53aa3e..4229e92f4d537 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
@@ -136,3 +136,54 @@ body: |
     %y:vrnov0 = COPY %x
     %z:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %y, %mask, %avl, 5 /* e32 */
 ...
+---
+name: copy_is_killed
+body: |
+  bb.0:
+    liveins: $x10, $x11, $x12
+    ; CHECK-LABEL: name: copy_is_killed
+    ; CHECK: liveins: $x10, $x11, $x12
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[PseudoVLM_V_B32_:%[0-9]+]]:vr = PseudoVLM_V_B32 $noreg, [[COPY2]], -1, 0 /* e8 */, 3 /* ta, ma */ :: (load unknown-size, align 1)
+    ; CHECK-NEXT: [[PseudoVLM_V_B32_1:%[0-9]+]]:vr = PseudoVLM_V_B32 $noreg, [[COPY1]], -1, 0 /* e8 */, 3 /* ta, ma */ :: (load unknown-size, align 1)
+    ; CHECK-NEXT: [[PseudoVLM_V_B32_2:%[0-9]+]]:vr = PseudoVLM_V_B32 $noreg, [[COPY]], -1, 0 /* e8 */, 3 /* ta, ma */ :: (load unknown-size, align 1)
+    ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vmv0 = COPY [[PseudoVLM_V_B32_]]
+    ; CHECK-NEXT: [[PseudoVMERGE_VIM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, [[PseudoVMV_V_I_M1_]], 1, killed [[COPY3]], -1, 5 /* e32 */
+    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vr = COPY [[PseudoVMERGE_VIM_M1_]]
+    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vmv0 = COPY [[PseudoVLM_V_B32_2]]
+    ; CHECK-NEXT: [[PseudoVMERGE_VIM_M1_1:%[0-9]+]]:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, [[PseudoVMV_V_I_M1_]], 1, killed [[COPY5]], -1, 5 /* e32 */
+    ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1 $noreg, [[PseudoVMERGE_VIM_M1_]], [[PseudoVMERGE_VIM_M1_1]], -1, 5 /* e32 */, 3 /* ta, ma */
+    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vrnov0 = COPY [[PseudoVADD_VV_M1_]]
+    ; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 $noreg, [[PseudoVMERGE_VIM_M1_]], [[PseudoVMERGE_VIM_M1_1]], -1, 5 /* e32 */, 3 /* ta, ma */
+    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vmv0 = COPY [[PseudoVLM_V_B32_1]]
+    ; CHECK-NEXT: [[PseudoVOR_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVOR_VV_M1_MASK [[PseudoVADD_VV_M1_]], [[COPY6]], killed [[COPY4]], [[COPY7]], -1, 5 /* e32 */, 1 /* ta, mu */
+    ; CHECK-NEXT: [[PseudoVOR_VV_M1_:%[0-9]+]]:vr = PseudoVOR_VV_M1 $noreg, killed [[PseudoVOR_VV_M1_MASK]], killed [[PseudoVSUB_VV_M1_]], -1, 5 /* e32 */, 3 /* ta, ma */
+    ; CHECK-NEXT: $v8 = COPY [[PseudoVOR_VV_M1_]]
+    ; CHECK-NEXT: PseudoRET implicit $v8
+    %2:gpr = COPY $x12
+    %1:gpr = COPY $x11
+    %0:gpr = COPY $x10
+    %3:vr = PseudoVLM_V_B32 $noreg, %0:gpr, -1, 0, 3 :: (load unknown-size, align 1)
+    %4:vr = PseudoVLM_V_B32 $noreg, %1:gpr, -1, 0, 3 :: (load unknown-size, align 1)
+    %5:vr = PseudoVLM_V_B32 $noreg, %2:gpr, -1, 0, 3 :: (load unknown-size, align 1)
+    %6:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 5, 0
+    %8:vmv0 = COPY %3:vr
+    %7:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %6:vrnov0, 1, killed %8:vmv0, -1, 5
+    %9:vr = COPY %7:vrnov0
+    %11:vmv0 = COPY %5:vr
+    %10:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %6:vrnov0, 1, killed %11:vmv0, -1, 5
+    %12:vr = PseudoVADD_VV_M1 $noreg, %7:vrnov0, %10:vrnov0, -1, 5, 3
+    %13:vrnov0 = COPY killed %12:vr
+    %14:vr = PseudoVSUB_VV_M1 $noreg, %7:vrnov0, %10:vrnov0, -1, 5, 3
+    %15:vrnov0 = PseudoVOR_VV_M1 $noreg, %13:vrnov0, killed %9:vr, -1, 5, 3
+    %17:vmv0 = COPY %4:vr
+    %16:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %13:vrnov0, killed %15:vrnov0, killed %17:vmv0, -1, 5
+    %18:vr = PseudoVOR_VV_M1 $noreg, killed %16:vrnov0, killed %14:vr, -1, 5, 3
+    $v8 = COPY %18:vr
+    PseudoRET implicit $v8
+...
+

``````````

</details>


https://github.com/llvm/llvm-project/pull/170438