[llvm] [AArch64] Optimize more floating-point round+convert combinations into fcvt instructions (PR #170018)

[via llvm-commits]

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@@ -5830,6 +5830,33 @@ multiclass SIMDTwoVectorFPToIntSatPats<SDNode to_int_sat, SDNode to_int_sat_gi,
 defm : SIMDTwoVectorFPToIntSatPats<fp_to_sint_sat, fp_to_sint_sat_gi, "FCVTZS">;
 defm : SIMDTwoVectorFPToIntSatPats<fp_to_uint_sat, fp_to_uint_sat_gi, "FCVTZU">;
 
+// Fused round + convert to int patterns for vectors
+multiclass SIMDTwoVectorFPToIntRoundPats<SDNode to_int, SDNode round, string INST> {
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valadaptive wrote:

Not sure what happened. I redid this part to just copy all the patterns from `SIMDTwoVectorFPToIntSatPats`, but with the additional non-saturating ops and the rounding function as part of the patterns. I'll admit I'm not sure what the GlobalISel versions are (the `_gi` suffixed ones) but they're present too now.

Is there any logic to why some saturating ops are part of their own multiclass (`FPToIntegerIntPats` + `FPToIntegerSatPats`) and some are part of the same multiclass as their non-saturating counterparts (`FPToIntegerPats`)?

https://github.com/llvm/llvm-project/pull/170018