[llvm] [RISCV] Update P extension to the 018 version of the spec. (PR #170399)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 2 17:54:36 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
https://www.jhauser.us/RISCV/ext-P/
---
Patch is 84.73 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/170399.diff
18 Files Affected:
- (modified) llvm/docs/RISCVUsage.rst (+3)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+1-21)
- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+3-25)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+41-48)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZb.td (+17-26)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+2-2)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rv32p.ll (+2-668)
- (modified) llvm/test/CodeGen/RISCV/rv64p.ll (-629)
- (modified) llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll (+12-12)
- (modified) llvm/test/MC/RISCV/attribute-arch.s (+4-4)
- (modified) llvm/test/MC/RISCV/rv32i-invalid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32p-invalid.s (+5-4)
- (modified) llvm/test/MC/RISCV/rv32p-valid.s (+50-77)
- (modified) llvm/test/MC/RISCV/rv64p-valid.s (+34-64)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1-1)
``````````diff
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a21f03d389444..8f360a97ba9d9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -333,6 +333,9 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp
The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
+``experimental-p``
+ LLVM implements the `018 draft specification <https://www.jhauser.us/RISCV/ext-P/>`__.
+
``experimental-zalasr``
LLVM implements the `0.9 draft specification <https://github.com/riscv/riscv-zalasr/releases/tag/v0.9>`__.
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4fc776fcdeb9a..20b9af5a5ae0b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1106,38 +1106,18 @@ def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
// Packed SIMD Extensions
def FeatureStdExtP
- : RISCVExperimentalExtension<0, 15,
+ : RISCVExperimentalExtension<0, 18,
"'Base P' (Packed SIMD)">;
def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">,
AssemblerPredicate<(all_of FeatureStdExtP),
"'Base P' (Packed SIMD)">;
-def HasStdExtZbaOrP
- : Predicate<"Subtarget->hasStdExtZba() || Subtarget->hasStdExtP()">,
- AssemblerPredicate<(any_of FeatureStdExtZba, FeatureStdExtP),
- "'Zba' (Address Generation Instructions) or "
- "'Base P' (Packed-SIMD)">;
-
-def HasStdExtZbbOrP
- : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtP()">,
- AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtP),
- "'Zbb' (Basic Bit-Manipulation) or "
- "'Base P' (Packed-SIMD)">;
-
def HasStdExtZbkbOrP
: Predicate<"Subtarget->hasStdExtZbkb() || Subtarget->hasStdExtP()">,
AssemblerPredicate<(any_of FeatureStdExtZbkb, FeatureStdExtP),
"'Zbkb' (Bitmanip instructions for Cryptography) or "
"'Base P' (Packed-SIMD)">;
-def HasStdExtZbbOrZbkbOrP
- : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb() || "
- "Subtarget->hasStdExtP()">,
- AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb, FeatureStdExtP),
- "'Zbb' (Basic Bit-Manipulation) or "
- "'Zbkb' (Bitmanip instructions for Cryptography) or "
- "'Base P' (Packed-SIMD)">;
-
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 7cf6f203fda89..9bc0d1280d968 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1893,7 +1893,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
0);
MachineSDNode *PackDH = CurDAG->getMachineNode(
- RISCV::PPACK_DH, DL, MVT::Untyped, {RegPair0, RegPair1});
+ RISCV::PPAIRE_DB, DL, MVT::Untyped, {RegPair0, RegPair1});
SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL,
MVT::i32, SDValue(PackDH, 0));
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ab2652eac3823..f7db690030eed 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -336,9 +336,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
- if (!Subtarget.hasStdExtZbb() && !Subtarget.hasStdExtP() &&
- !Subtarget.hasVendorXTHeadBb() && !Subtarget.hasVendorXqcibm() &&
- !Subtarget.hasVendorXAndesPerf() &&
+ if (!Subtarget.hasStdExtZbb() && !Subtarget.hasVendorXTHeadBb() &&
+ !Subtarget.hasVendorXqcibm() && !Subtarget.hasVendorXAndesPerf() &&
!(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit()))
setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::i8, MVT::i16}, Expand);
@@ -411,7 +410,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
}
- if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtP() ||
+ if (Subtarget.hasStdExtZbb() ||
(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit())) {
setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT,
Legal);
@@ -422,9 +421,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
} else {
setOperationAction(ISD::CTTZ, XLenVT, Expand);
- // If have a CLZW, but not CTZW, custom promote i32.
- if (Subtarget.hasStdExtP() && Subtarget.is64Bit())
- setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
}
if (!Subtarget.hasCPOPLike()) {
@@ -14997,24 +14993,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
bool IsCTZ =
N->getOpcode() == ISD::CTTZ || N->getOpcode() == ISD::CTTZ_ZERO_UNDEF;
- // Without Zbb, lower as 32 - clzw(~X & (X-1))
- if (IsCTZ && !Subtarget.hasStdExtZbb()) {
- assert(Subtarget.hasStdExtP());
-
- NewOp0 = DAG.getFreeze(NewOp0);
- SDValue Not = DAG.getNOT(DL, NewOp0, MVT::i64);
- SDValue Minus1 = DAG.getNode(ISD::SUB, DL, MVT::i64, NewOp0,
- DAG.getConstant(1, DL, MVT::i64));
- SDValue And = DAG.getNode(ISD::AND, DL, MVT::i64, Not, Minus1);
- SDValue CLZW = DAG.getNode(RISCVISD::CLZW, DL, MVT::i64, And);
- SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i64,
- DAG.getConstant(32, DL, MVT::i64), CLZW);
- SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, Sub,
- DAG.getValueType(MVT::i32));
- Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
- return;
- }
-
unsigned Opc = IsCTZ ? RISCVISD::CTZW : RISCVISD::CLZW;
SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp0);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 599358368594f..4515a8d0f42d0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -632,8 +632,8 @@ let Predicates = [HasStdExtP] in {
def PSUB_H : RVPBinary_rr<0b1000, 0b00, 0b000, "psub.h">;
def PSUB_B : RVPBinary_rr<0b1000, 0b10, 0b000, "psub.b">;
- def PDIF_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pdif.h">;
- def PDIF_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pdif.b">;
+ def PABD_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pabd.h">;
+ def PABD_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pabd.b">;
def PSSUB_H : RVPBinary_rr<0b1010, 0b00, 0b000, "pssub.h">;
def PSSUB_B : RVPBinary_rr<0b1010, 0b10, 0b000, "pssub.b">;
@@ -641,8 +641,8 @@ let Predicates = [HasStdExtP] in {
def PASUB_H : RVPBinary_rr<0b1011, 0b00, 0b000, "pasub.h">;
def PASUB_B : RVPBinary_rr<0b1011, 0b10, 0b000, "pasub.b">;
- def PDIFU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pdifu.h">;
- def PDIFU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pdifu.b">;
+ def PABDU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pabdu.h">;
+ def PABDU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pabdu.b">;
def PSSUBU_H : RVPBinary_rr<0b1110, 0b00, 0b000, "pssubu.h">;
def PSSUBU_B : RVPBinary_rr<0b1110, 0b10, 0b000, "pssubu.b">;
@@ -700,9 +700,9 @@ let Predicates = [HasStdExtP] in {
def SRX : RVPTernary_rrr<0b0101, 0b11, 0b001, "srx">;
def PMULU_H_B01 : RVPBinary_rr<0b0110, 0b00, 0b001, "pmulu.h.b01">;
- def PDIFSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pdifsumu.b">;
+ def PABDSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pabdsumu.b">;
- def PDIFSUMAU_B : RVPTernary_rrr<0b0111, 0b10, 0b001, "pdifsumau.b">;
+ def PABDSUMAU_B : RVPTernary_rrr<0b0111, 0b10, 0b001, "pabdsumau.b">;
} // Predicates = [HasStdExtP]
let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
def MUL_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "mul.h01">;
@@ -832,32 +832,25 @@ let Predicates = [HasStdExtP, IsRV64] in {
// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.
// Here we include the 0 in the f field to reduce number of tablegen classes.
let Predicates = [HasStdExtP] in {
- def PPACK_H : RVPBinary_rr<0b0000, 0b00, 0b100, "ppack.h">;
+ def PPAIRE_B : RVPBinary_rr<0b0000, 0b00, 0b100, "ppaire.b">;
- def PPACKBT_H : RVPBinary_rr<0b0010, 0b00, 0b100, "ppackbt.h">;
+ def PPAIREO_B : RVPBinary_rr<0b0010, 0b00, 0b100, "ppaireo.b">;
+ def PPAIREO_H : RVPBinary_rr<0b0010, 0b01, 0b100, "ppaireo.h">;
- def PPACKTB_H : RVPBinary_rr<0b0100, 0b00, 0b100, "ppacktb.h">;
+ def PPAIROE_B : RVPBinary_rr<0b0100, 0b00, 0b100, "ppairoe.b">;
+ def PPAIROE_H : RVPBinary_rr<0b0100, 0b01, 0b100, "ppairoe.h">;
- def PPACKT_H : RVPBinary_rr<0b0110, 0b00, 0b100, "ppackt.h">;
+ def PPAIRO_B : RVPBinary_rr<0b0110, 0b00, 0b100, "ppairo.b">;
+ def PPAIRO_H : RVPBinary_rr<0b0110, 0b01, 0b100, "ppairo.h">;
} // Predicates = [HasStdExtP]
-let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
- def PACKBT_RV32 : RVPBinary_rr<0b0010, 0b01, 0b100, "packbt">;
-
- def PACKTB_RV32 : RVPBinary_rr<0b0100, 0b01, 0b100, "packtb">;
-
- def PACKT_RV32 : RVPBinary_rr<0b0110, 0b01, 0b100, "packt">;
-} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
let Predicates = [HasStdExtP, IsRV64] in {
- def PPACK_W : RVPBinary_rr<0b0000, 0b01, 0b100, "ppack.w">;
+ def PPAIRE_H : RVPBinary_rr<0b0000, 0b01, 0b100, "ppaire.h">;
- def PPACKBT_W : RVPBinary_rr<0b0010, 0b01, 0b100, "ppackbt.w">;
- def PACKBT_RV64 : RVPBinary_rr<0b0010, 0b11, 0b100, "packbt">;
+ def PPAIREO_W : RVPBinary_rr<0b0010, 0b11, 0b100, "ppaireo.w">;
- def PPACKTB_W : RVPBinary_rr<0b0100, 0b01, 0b100, "ppacktb.w">;
- def PACKTB_RV64 : RVPBinary_rr<0b0100, 0b11, 0b100, "packtb">;
+ def PPAIROE_W : RVPBinary_rr<0b0100, 0b11, 0b100, "ppairoe.w">;
- def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">;
- def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">;
+ def PPAIRO_W : RVPBinary_rr<0b0110, 0b11, 0b100, "ppairo.w">;
} // Predicates = [HasStdExtP, IsRV64]
let Predicates = [HasStdExtP] in {
@@ -1385,8 +1378,8 @@ let Predicates = [HasStdExtP, IsRV32] in {
def PSUB_DB : RVPPairBinary_rr<0b1000, 0b10, "psub.db">;
def SUBD : RVPPairBinary_rr<0b1000, 0b11, "subd">;
- def PDIF_DH : RVPPairBinary_rr<0b1001, 0b00, "pdif.dh">;
- def PDIF_DB : RVPPairBinary_rr<0b1001, 0b10, "pdif.db">;
+ def PABD_DH : RVPPairBinary_rr<0b1001, 0b00, "pabd.dh">;
+ def PABD_DB : RVPPairBinary_rr<0b1001, 0b10, "pabd.db">;
def PSSUB_DH : RVPPairBinary_rr<0b1010, 0b00, "pssub.dh">;
def PSSUB_DW : RVPPairBinary_rr<0b1010, 0b01, "pssub.dw">;
@@ -1396,8 +1389,8 @@ let Predicates = [HasStdExtP, IsRV32] in {
def PASUB_DW : RVPPairBinary_rr<0b1011, 0b01, "pasub.dw">;
def PASUB_DB : RVPPairBinary_rr<0b1011, 0b10, "pasub.db">;
- def PDIFU_DH : RVPPairBinary_rr<0b1101, 0b00, "pdifu.dh">;
- def PDIFU_DB : RVPPairBinary_rr<0b1101, 0b10, "pdifu.db">;
+ def PABDU_DH : RVPPairBinary_rr<0b1101, 0b00, "pabdu.dh">;
+ def PABDU_DB : RVPPairBinary_rr<0b1101, 0b10, "pabdu.db">;
def PSSUBU_DH : RVPPairBinary_rr<0b1110, 0b00, "pssubu.dh">;
def PSSUBU_DW : RVPPairBinary_rr<0b1110, 0b01, "pssubu.dw">;
@@ -1413,17 +1406,17 @@ let Predicates = [HasStdExtP, IsRV32] in {
def PSSH1SADD_DH : RVPPairBinaryShift_rr<0b011, 0b00, "pssh1sadd.dh">;
def PSSH1SADD_DW : RVPPairBinaryShift_rr<0b011, 0b01, "pssh1sadd.dw">;
- def PPACK_DH : RVPPairBinaryPack_rr<0b000, 0b00, "ppack.dh">;
- def PPACK_DW : RVPPairBinaryPack_rr<0b000, 0b01, "ppack.dw">;
+ def PPAIRE_DB : RVPPairBinaryPack_rr<0b000, 0b00, "ppaire.db">;
+ def PPAIRE_DH : RVPPairBinaryPack_rr<0b000, 0b01, "ppaire.dh">;
- def PPACKBT_DH : RVPPairBinaryPack_rr<0b001, 0b00, "ppackbt.dh">;
- def PPACKBT_DW : RVPPairBinaryPack_rr<0b001, 0b01, "ppackbt.dw">;
+ def PPAIREO_DB : RVPPairBinaryPack_rr<0b001, 0b00, "ppaireo.db">;
+ def PPAIREO_DH : RVPPairBinaryPack_rr<0b001, 0b01, "ppaireo.dh">;
- def PPACKTB_DH : RVPPairBinaryPack_rr<0b010, 0b00, "ppacktb.dh">;
- def PPACKTB_DW : RVPPairBinaryPack_rr<0b010, 0b01, "ppacktb.dw">;
+ def PPAIROE_DB : RVPPairBinaryPack_rr<0b010, 0b00, "ppairoe.db">;
+ def PPAIROE_DH : RVPPairBinaryPack_rr<0b010, 0b01, "ppairoe.dh">;
- def PPACKT_DH : RVPPairBinaryPack_rr<0b011, 0b00, "ppackt.dh">;
- def PPACKT_DW : RVPPairBinaryPack_rr<0b011, 0b01, "ppackt.dw">;
+ def PPAIRO_DB : RVPPairBinaryPack_rr<0b011, 0b00, "ppairo.db">;
+ def PPAIRO_DH : RVPPairBinaryPack_rr<0b011, 0b01, "ppairo.dh">;
def PAS_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b00, "pas.dhx">;
def PSA_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b10, "psa.dhx">;
@@ -1511,15 +1504,15 @@ let Predicates = [HasStdExtP] in {
def: Pat<(XLenVecI16VT (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_H GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_H GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>;
-
+
// 8-bit absolute difference patterns
- def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PDIF_B GPR:$rs1, GPR:$rs2)>;
- def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PDIFU_B GPR:$rs1, GPR:$rs2)>;
-
+ def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PABD_B GPR:$rs1, GPR:$rs2)>;
+ def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_B GPR:$rs1, GPR:$rs2)>;
+
// 16-bit absolute difference patterns
- def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PDIF_H GPR:$rs1, GPR:$rs2)>;
- def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PDIFU_H GPR:$rs1, GPR:$rs2)>;
-
+ def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PABD_H GPR:$rs1, GPR:$rs2)>;
+ def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_H GPR:$rs1, GPR:$rs2)>;
+
// 8-bit logical shift left patterns
def: Pat<(XLenVecI8VT (shl GPR:$rs1, (XLenVecI8VT (splat_vector uimm3:$shamt)))),
(PSLLI_B GPR:$rs1, uimm3:$shamt)>;
@@ -1602,22 +1595,22 @@ let Predicates = [HasStdExtP, IsRV64] in {
(XLenVT GPR:$c), (XLenVT GPR:$d),
(XLenVT undef), (XLenVT undef),
(XLenVT undef), (XLenVT undef))),
- (PPACK_W (PPACK_H GPR:$a, GPR:$b), (PPACK_H GPR:$c, GPR:$d))>;
+ (PPAIRE_H (PPAIRE_B GPR:$a, GPR:$b), (PPAIRE_B GPR:$c, GPR:$d))>;
def : Pat<(v8i8 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b),
(XLenVT GPR:$c), (XLenVT GPR:$d),
(XLenVT GPR:$e), (XLenVT GPR:$f),
(XLenVT GPR:$g), (XLenVT GPR:$h))),
- (PACK(PPACK_W (PPACK_H GPR:$a, GPR:$b), (PPACK_H GPR:$c, GPR:$d)),
- (PPACK_W (PPACK_H GPR:$e, GPR:$f), (PPACK_H GPR:$g, GPR:$h)))>;
+ (PACK (PPAIRE_H (PPAIRE_B GPR:$a, GPR:$b), (PPAIRE_B GPR:$c, GPR:$d)),
+ (PPAIRE_H (PPAIRE_B GPR:$e, GPR:$f), (PPAIRE_B GPR:$g, GPR:$h)))>;
def : Pat<(v4i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b),
(XLenVT undef), (XLenVT undef))),
- (PPACK_W GPR:$a, GPR:$b)>;
+ (PPAIRE_H GPR:$a, GPR:$b)>;
def : Pat<(v4i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b),
(XLenVT GPR:$c), (XLenVT GPR:$d))),
- (PACK (PPACK_W GPR:$a, GPR:$b), (PPACK_W GPR:$c, GPR:$d))>;
+ (PACK (PPAIRE_H GPR:$a, GPR:$b), (PPAIRE_H GPR:$c, GPR:$d))>;
def : Pat<(v2i32 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))),
(PACK GPR:$a, GPR:$b)>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 5429c2a1a21b0..673894db56129 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -276,10 +276,9 @@ def XNOR : ALU_rr<0b0100000, 0b100, "xnor", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
} // Predicates = [HasStdExtZbbOrZbkb]
-let Predicates = [HasStdExtZbaOrP] in
+let Predicates = [HasStdExtZba] in {
def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
-let Predicates = [HasStdExtZba] in {
def SH2ADD : ALU_rr<0b0010000, 0b100, "sh2add">,
Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
@@ -351,32 +350,30 @@ def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">,
Sched<[WriteXPERM, ReadXPERM, ReadXPERM]>;
} // Predicates = [HasStdExtZbkx]
-let Predicates = [HasStdExtZbbOrP], IsSignExtendingOpW = 1 in
+let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
def CLZ : Unary_r<0b011000000000, 0b001, "clz">,
Sched<[WriteCLZ, ReadCLZ]>;
-let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
def CTZ : Unary_r<0b011000000001, 0b001, "ctz">,
Sched<[WriteCTZ, ReadCTZ]>;
def CPOP : Unary_r<0b011000000010, 0b001, "cpop">,
Sched<[WriteCPOP, ReadCPOP]>;
} // Predicates = [HasStdExtZbb]
-let Predicates = [HasStdExtZbbOrP, IsRV64], IsSignExtendingOpW = 1 in
+let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
def CLZW : UnaryW_r<0b011000000000, 0b001, "clzw">,
Sched<[WriteCLZ32, ReadCLZ32]>;
-let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
def CTZW : UnaryW_r<0b011000000001, 0b001, "ctzw">,
Sched<[WriteCTZ32, ReadCTZ32]>;
def CPOPW : UnaryW_r<0b011000000010, 0b001, "cpopw">,
Sched<[WriteCPOP32, ReadCPOP32]>;
} // Predicates = [HasStdExtZbb, IsRV64]
-let Predicates = [HasStdExtZbbOrP], IsSignExtendingOpW = 1 in {
+let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
def SEXT_B : Unary_r<0b011000000100, 0b001, "sext.b">,
Sched<[WriteIALU, ReadIALU]>;
def SEXT_H : Unary_r<0b011000000101, 0b001, "sext.h">,
Sched<[WriteIALU, ReadIALU]>;
-} // Predicates = [HasStdExtZbbOrP]
+} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbc] in {
def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr", Commutable=1>,
@@ -390,7 +387,7 @@ def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", Commutable=1>,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
} // Predicates = [HasStdExtZbcOrZbkc]
-let Predicates = [HasStdExtZbbOrP] in {
+let Predicates = [HasStdExtZbb] in {
def MIN : ALU_rr<0b0000101, 0b100, "min", Commutable=1>,
Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>;
def MINU : ALU_rr<0b0000101, 0b101, "minu", Commutable=1>,
@@ -399,7 +396,7 @@ def MAX : ALU_rr<0b0000101, 0b110, "max", Commutable=1>,
Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>;
def MAXU : ALU_rr<0b0000101, 0b111, "maxu", Commutable=1>,
Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>;
-} // Predicates = [HasStdExtZbbOrP]
+} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbkbOrP] in
def PACK : ALU_rr<0b0000100, 0b100, "pack">,
@@ -424,15 +421,15 @@ def ZEXT_H_RV64 : RVBUnaryR<0b0000100, 0b100, OPC_OP_32, "zext.h">,
Sched<[WriteIALU, ReadIALU]>;
} // Predicates = [HasStdExtZbb, IsRV64]
-let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32] in {
+let...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/170399
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