[llvm] [RISCV] Use vsetivli instead of `x0,x0` form to retain SEW/LMUL when AVL is imm (PR #169307)

[Craig Topper via llvm-commits]

================
@@ -3767,10 +3762,9 @@ define <16 x i32> @PR159294_zext(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
 ; RVA22U64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; RVA22U64-NEXT:    vmv.v.i v8, 0
 ; RVA22U64-NEXT:    zext.h a1, a1
-; RVA22U64-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
+; RVA22U64-NEXT:    vsetivli zero, 2, e64, m1, tu, ma
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topperc wrote:

Is the coalescing step missing this because of the `RISCVInstrInfo::isVLPreservingConfig` check here?

```
    if (Used.VLZeroness) {                                                       
      if (RISCVInstrInfo::isVLPreservingConfig(PrevMI))                          
        return false;                                                            
      if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),    
                                                       LIS))                     
        return false;                                                            
    } 
```

Could we try to find the vsetvli we're preserving the VL from instead of giving up?

https://github.com/llvm/llvm-project/pull/169307