[llvm] [AMDGPU] Prevent folding of flat_scr_base_hi into a 64-bit SALU (PR #170373)

[Matt Arsenault via llvm-commits]

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@@ -6256,6 +6256,17 @@ bool SIInstrInfo::isLegalRegOperand(const MachineInstr &MI, unsigned OpIdx,
       (int)OpIdx == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) &&
       RI.isSGPRReg(MRI, MO.getReg()))
     return false;
+
+  if (ST.hasFlatScratchHiInB64InstHazard() &&
+      MO.getReg() == AMDGPU::SRC_FLAT_SCRATCH_BASE_HI && isSALU(MI)) {
+    if (const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::sdst)) {
+      if (AMDGPU::getRegBitWidth(*MRI.getRegClass(Dst->getReg())) == 64)
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arsenm wrote:

We do and should cover missed cases. The operand legality is primarily a verification function 

https://github.com/llvm/llvm-project/pull/170373