[llvm] [RISCV] Introduce a new tune feature string syntax and its parser (PR #168160)

[Min-Yih Hsu via llvm-commits]

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@@ -1792,44 +1799,54 @@ def TuneNLogNVRGather
                       "Has vrgather.vv with LMUL*log2(LMUL) latency">;
 
 def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
-    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
+    "UsePostRAScheduler", "true", "Schedule again after register allocation">,
+    RISCVSimpleTuneFeature;
 
 def TuneDisableMISchedLoadClustering : SubtargetFeature<"disable-misched-load-clustering",
-    "EnableMISchedLoadClustering", "false", "Disable load clustering in the machine scheduler">;
+    "EnableMISchedLoadClustering", "false", "Disable load clustering in the machine scheduler">,
+    RISCVTuneFeature<"disable-misched-load-clustering", "enable-misched-load-clustering">;
 
 def TuneDisableMISchedStoreClustering : SubtargetFeature<"disable-misched-store-clustering",
-    "EnableMISchedStoreClustering", "false", "Disable store clustering in the machine scheduler">;
+    "EnableMISchedStoreClustering", "false", "Disable store clustering in the machine scheduler">,
+    RISCVTuneFeature<"disable-misched-store-clustering", "enable-misched-store-clustering">;
 
 def TuneDisablePostMISchedLoadClustering : SubtargetFeature<"disable-postmisched-load-clustering",
-    "EnablePostMISchedLoadClustering", "false", "Disable PostRA load clustering in the machine scheduler">;
+    "EnablePostMISchedLoadClustering", "false", "Disable PostRA load clustering in the machine scheduler">,
+    RISCVTuneFeature<"disable-postmisched-load-clustering", "enable-postmisched-load-clustering">;
 
 def TuneDisablePostMISchedStoreClustering : SubtargetFeature<"disable-postmisched-store-clustering",
-    "EnablePostMISchedStoreClustering", "false", "Disable PostRA store clustering in the machine scheduler">;
+    "EnablePostMISchedStoreClustering", "false", "Disable PostRA store clustering in the machine scheduler">,
+    RISCVTuneFeature<"disable-postmisched-store-clustering", "enable-postmisched-store-clustering">;
 
 def TuneDisableLatencySchedHeuristic
     : SubtargetFeature<"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
-                       "Disable latency scheduling heuristic">;
+                       "Disable latency scheduling heuristic">,
+      RISCVTuneFeature<"disable-latency-sched-heuristic", "enable-latency-sched-heuristic">;
 
 def TunePredictableSelectIsExpensive
     : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
-                       "Prefer likely predicted branches over selects">;
+                       "Prefer likely predicted branches over selects">,
+      RISCVSimpleTuneFeature;
 
 def TuneOptimizedZeroStrideLoad
    : SubtargetFeature<"optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
                       "true", "Optimized (perform fewer memory operations)"
-                      "zero-stride vector load">;
+                      "zero-stride vector load">,
+      RISCVSimpleTuneFeature;
----------------
mshockwave wrote:

hmmm this one is a bit tricky because SiFive7 is using `VLDSX0Pred` to predicate zero-stride load, but that SchedPredicate checks MCInst rather than subtarget feature. Theoretically we can connect `VLDSX0Pred` to `optimized-zero-stride-load` in addition to its current MCInst predicate.

https://github.com/llvm/llvm-project/pull/168160