[llvm] [RISCV] LMUL lists for indexed and strided loads (PR #169756)

[Petr Penzin via llvm-commits]

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@@ -19,6 +19,14 @@ defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
 defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
 // Used for widening floating-point Reduction as it doesn't contain MF8.
 defvar SchedMxListFWRed = SchedMxListF;
+// Used for indexed and strided loads of 8 bit lanes, same as full MX list
+defvar SchedMxListDS8 = SchedMxList;
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ppenzin wrote:

Focused on wrong common letter, sorry

https://github.com/llvm/llvm-project/pull/169756