[llvm] AMDGPU/GlobalISel: Report RegBankLegalize errors using reportGISelFailure (PR #169918)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 2 09:44:46 PST 2025
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/169918
>From d202056782cf9eb36dde1275893451f3e4db49c4 Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Fri, 28 Nov 2025 14:11:07 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Report RegBankLegalize errors using
reportGISelFailure
Use standard GlobalISel error reporting with reportGISelFailure
and pass returning false instead of llvm_unreachable.
Also enables -global-isel-abort=0 or 2 for -global-isel -new-reg-bank-select.
Note: new-reg-bank-select with abort 0 or 2 runs LCSSA,
while "intended use" without abort or with abort 1 does not run LCSSA.
---
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 6 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 199 ++++++++++++------
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 39 ++--
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 27 +--
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 4 +-
5 files changed, 175 insertions(+), 100 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index 396d64625fb5c..839120da89711 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -435,7 +435,8 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
unsigned Opc = MI->getOpcode();
// Insert point for use operands needs some calculation.
if (Opc == AMDGPU::G_PHI) {
- RBLHelper.applyMappingPHI(*MI);
+ if (!RBLHelper.applyMappingPHI(*MI))
+ return false;
continue;
}
@@ -466,7 +467,8 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
// S1 rules are in RegBankLegalizeRules.
}
- RBLHelper.findRuleAndApplyMapping(*MI);
+ if (!RBLHelper.findRuleAndApplyMapping(*MI))
+ return false;
}
// Sgpr S1 clean up combines:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 123fc5bf37a19..cc31d7d5c55ac 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -32,28 +32,48 @@ using namespace AMDGPU;
RegBankLegalizeHelper::RegBankLegalizeHelper(
MachineIRBuilder &B, const MachineUniformityInfo &MUI,
const RegisterBankInfo &RBI, const RegBankLegalizeRules &RBLRules)
- : ST(B.getMF().getSubtarget<GCNSubtarget>()), B(B), MRI(*B.getMRI()),
- MUI(MUI), RBI(RBI), RBLRules(RBLRules), IsWave32(ST.isWave32()),
+ : MF(B.getMF()), ST(MF.getSubtarget<GCNSubtarget>()), B(B),
+ MRI(*B.getMRI()), MUI(MUI), RBI(RBI), MORE(MF, nullptr),
+ RBLRules(RBLRules), IsWave32(ST.isWave32()),
SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)),
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {}
-void RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
- const SetOfRulesForOpcode &RuleSet = RBLRules.getRulesForOpc(MI);
- const RegBankLLTMapping &Mapping = RuleSet.findMappingForMI(MI, MRI, MUI);
+bool RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
+ const SetOfRulesForOpcode *RuleSet = RBLRules.getRulesForOpc(MI);
+ if (!RuleSet) {
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "No AMDGPU RegBankLegalize rules defined for opcode",
+ MI);
+ return false;
+ }
+
+ const RegBankLLTMapping *Mapping = RuleSet->findMappingForMI(MI, MRI, MUI);
+ if (!Mapping) {
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: none of the rules defined with "
+ "'Any' for MI's opcode matched MI",
+ MI);
+ return false;
+ }
SmallSet<Register, 4> WaterfallSgprs;
unsigned OpIdx = 0;
- if (Mapping.DstOpMapping.size() > 0) {
+ if (Mapping->DstOpMapping.size() > 0) {
B.setInsertPt(*MI.getParent(), std::next(MI.getIterator()));
- applyMappingDst(MI, OpIdx, Mapping.DstOpMapping);
+ if (!applyMappingDst(MI, OpIdx, Mapping->DstOpMapping))
+ return false;
}
- if (Mapping.SrcOpMapping.size() > 0) {
+ if (Mapping->SrcOpMapping.size() > 0) {
B.setInstr(MI);
- applyMappingSrc(MI, OpIdx, Mapping.SrcOpMapping, WaterfallSgprs);
+ if (!applyMappingSrc(MI, OpIdx, Mapping->SrcOpMapping, WaterfallSgprs))
+ return false;
}
- lower(MI, Mapping, WaterfallSgprs);
+ if (!lower(MI, *Mapping, WaterfallSgprs))
+ return false;
+
+ return true;
}
bool RegBankLegalizeHelper::executeInWaterfallLoop(
@@ -274,7 +294,7 @@ bool RegBankLegalizeHelper::executeInWaterfallLoop(
return true;
}
-void RegBankLegalizeHelper::splitLoad(MachineInstr &MI,
+bool RegBankLegalizeHelper::splitLoad(MachineInstr &MI,
ArrayRef<LLT> LLTBreakdown, LLT MergeTy) {
MachineFunction &MF = B.getMF();
assert(MI.getNumMemOperands() == 1);
@@ -322,9 +342,10 @@ void RegBankLegalizeHelper::splitLoad(MachineInstr &MI,
B.buildMergeLikeInstr(Dst, MergeTyParts);
}
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::widenLoad(MachineInstr &MI, LLT WideTy,
+bool RegBankLegalizeHelper::widenLoad(MachineInstr &MI, LLT WideTy,
LLT MergeTy) {
MachineFunction &MF = B.getMF();
assert(MI.getNumMemOperands() == 1);
@@ -350,9 +371,10 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI, LLT WideTy,
B.buildMergeLikeInstr(Dst, MergeTyParts);
}
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::widenMMOToS32(GAnyLoad &MI) const {
+bool RegBankLegalizeHelper::widenMMOToS32(GAnyLoad &MI) const {
Register Dst = MI.getDstReg();
Register Ptr = MI.getPointerReg();
MachineMemOperand &MMO = MI.getMMO();
@@ -376,9 +398,10 @@ void RegBankLegalizeHelper::widenMMOToS32(GAnyLoad &MI) const {
}
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
Register Src = MI.getOperand(1).getReg();
@@ -404,15 +427,22 @@ void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
Hi = B.buildUndef({VgprRB_S32});
break;
default:
- llvm_unreachable("Opcode not supported");
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: lowerVccExtToSel, Opcode not supported", MI);
+ return false;
}
B.buildMergeValues(Dst, {Lo.getReg(0), Hi.getReg(0)});
} else {
- llvm_unreachable("Type not supported");
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: lowerVccExtToSel, Type not supported", MI);
+ return false;
}
MI.eraseFromParent();
+ return true;
}
std::pair<Register, Register> RegBankLegalizeHelper::unpackZExt(Register Reg) {
@@ -444,7 +474,7 @@ RegBankLegalizeHelper::unpackAExtTruncS16(Register Reg) {
B.buildTrunc(SgprRB_S16, Hi32).getReg(0)};
}
-void RegBankLegalizeHelper::lowerUnpackBitShift(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerUnpackBitShift(MachineInstr &MI) {
Register Lo, Hi;
switch (MI.getOpcode()) {
case AMDGPU::G_SHL: {
@@ -469,13 +499,18 @@ void RegBankLegalizeHelper::lowerUnpackBitShift(MachineInstr &MI) {
break;
}
default:
- llvm_unreachable("Unpack lowering not implemented");
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: lowerUnpackBitShift, case not implemented",
+ MI);
+ return false;
}
B.buildBuildVectorTrunc(MI.getOperand(0).getReg(), {Lo, Hi});
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
Register Lo, Hi;
switch (MI.getOpcode()) {
case AMDGPU::G_SMIN:
@@ -501,13 +536,17 @@ void RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
break;
}
default:
- llvm_unreachable("Unpack min/max lowering not implemented");
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: lowerUnpackMinMax, case not implemented", MI);
+ return false;
}
B.buildBuildVectorTrunc(MI.getOperand(0).getReg(), {Lo, Hi});
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lowerUnpackAExt(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerUnpackAExt(MachineInstr &MI) {
auto [Op1Lo, Op1Hi] = unpackAExt(MI.getOperand(1).getReg());
auto [Op2Lo, Op2Hi] = unpackAExt(MI.getOperand(2).getReg());
auto ResLo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Op1Lo, Op2Lo});
@@ -515,6 +554,7 @@ void RegBankLegalizeHelper::lowerUnpackAExt(MachineInstr &MI) {
B.buildBuildVectorTrunc(MI.getOperand(0).getReg(),
{ResLo.getReg(0), ResHi.getReg(0)});
MI.eraseFromParent();
+ return true;
}
static bool isSignedBFE(MachineInstr &MI) {
@@ -524,7 +564,7 @@ static bool isSignedBFE(MachineInstr &MI) {
return MI.getOpcode() == AMDGPU::G_SBFX;
}
-void RegBankLegalizeHelper::lowerV_BFE(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerV_BFE(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
assert(MRI.getType(Dst) == LLT::scalar(64));
bool Signed = isSignedBFE(MI);
@@ -551,7 +591,7 @@ void RegBankLegalizeHelper::lowerV_BFE(MachineInstr &MI) {
auto SignBit = B.buildShl({VgprRB, S64}, SHRSrc, Amt);
B.buildInstr(SHROpc, {Dst}, {SignBit, Amt});
MI.eraseFromParent();
- return;
+ return true;
}
uint64_t WidthImm = ConstWidth->Value.getZExtValue();
@@ -581,9 +621,10 @@ void RegBankLegalizeHelper::lowerV_BFE(MachineInstr &MI) {
}
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
Register DstReg = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(DstReg);
bool Signed = isSignedBFE(MI);
@@ -609,14 +650,19 @@ void RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
auto S_BFE = B.buildInstr(Opc, {{SgprRB, Ty}},
{B.buildCopy(Ty, Src), B.buildCopy(S32, Src1)});
if (!constrainSelectedInstRegOperands(*S_BFE, *ST.getInstrInfo(),
- *ST.getRegisterInfo(), RBI))
- llvm_unreachable("failed to constrain BFE");
+ *ST.getRegisterInfo(), RBI)) {
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: lowerS_BFE, failed to constrain BFE", MI);
+ return false;
+ }
B.buildCopy(DstReg, S_BFE->getOperand(0).getReg());
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(Dst);
assert(DstTy == V4S16 || DstTy == V2S32 || DstTy == S64);
@@ -631,9 +677,10 @@ void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
B.buildInstr(Opc, {{VgprRB, Ty}}, {Op1.getReg(1), Op2.getReg(1)}, Flags);
B.buildMergeLikeInstr(Dst, {Lo, Hi});
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lowerSplitTo16(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerSplitTo16(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
assert(MRI.getType(Dst) == V2S16);
unsigned Opc = MI.getOpcode();
@@ -645,7 +692,7 @@ void RegBankLegalizeHelper::lowerSplitTo16(MachineInstr &MI) {
auto Hi = B.buildInstr(Opc, {SgprRB_S16}, {Op1Hi}, Flags);
B.buildMergeLikeInstr(Dst, {Lo, Hi});
MI.eraseFromParent();
- return;
+ return true;
}
assert(MI.getNumOperands() == 3);
@@ -655,9 +702,10 @@ void RegBankLegalizeHelper::lowerSplitTo16(MachineInstr &MI) {
auto Hi = B.buildInstr(Opc, {SgprRB_S16}, {Op1Hi, Op2Hi}, Flags);
B.buildMergeLikeInstr(Dst, {Lo, Hi});
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lowerSplitTo32Select(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerSplitTo32Select(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(Dst);
assert(DstTy == V4S16 || DstTy == V2S32 || DstTy == S64 ||
@@ -674,9 +722,10 @@ void RegBankLegalizeHelper::lowerSplitTo32Select(MachineInstr &MI) {
B.buildMergeLikeInstr(Dst, {Lo, Hi});
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lowerSplitTo32SExtInReg(MachineInstr &MI) {
+bool RegBankLegalizeHelper::lowerSplitTo32SExtInReg(MachineInstr &MI) {
auto Op1 = B.buildUnmerge(VgprRB_S32, MI.getOperand(1).getReg());
int Amt = MI.getOperand(2).getImm();
Register Lo, Hi;
@@ -701,9 +750,10 @@ void RegBankLegalizeHelper::lowerSplitTo32SExtInReg(MachineInstr &MI) {
B.buildMergeLikeInstr(MI.getOperand(0).getReg(), {Lo, Hi});
MI.eraseFromParent();
+ return true;
}
-void RegBankLegalizeHelper::lower(MachineInstr &MI,
+bool RegBankLegalizeHelper::lower(MachineInstr &MI,
const RegBankLLTMapping &Mapping,
SmallSet<Register, 4> &WaterfallSgprs) {
@@ -723,7 +773,7 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
B.buildSelect(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), True,
False);
MI.eraseFromParent();
- return;
+ return true;
}
case UnpackBitShift:
return lowerUnpackBitShift(MI);
@@ -750,20 +800,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
break;
}
default:
- llvm_unreachable("Unsuported Opcode in Ext32To64");
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: Ext32To64, unsuported opcode",
+ MI);
+ return false;
}
B.buildMergeLikeInstr(MI.getOperand(0).getReg(),
{MI.getOperand(1).getReg(), Hi});
MI.eraseFromParent();
- return;
+ return true;
}
case UniCstExt: {
uint64_t ConstVal = MI.getOperand(1).getCImm()->getZExtValue();
B.buildConstant(MI.getOperand(0).getReg(), ConstVal);
MI.eraseFromParent();
- return;
+ return true;
}
case VgprToVccCopy: {
Register Src = MI.getOperand(1).getReg();
@@ -787,7 +840,7 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
auto Zero = B.buildConstant({VgprRB, Ty}, 0);
B.buildICmp(CmpInst::ICMP_NE, MI.getOperand(0).getReg(), BoolSrc, Zero);
MI.eraseFromParent();
- return;
+ return true;
}
case V_BFE:
return lowerV_BFE(MI);
@@ -816,8 +869,10 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (Size / 128 == 4)
splitLoad(MI, {B128, B128, B128, B128});
else {
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("SplitLoad type not supported for MI");
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: SplitLoad, unsuported type",
+ MI);
+ return false;
}
}
// 64 and 32 bit load
@@ -828,10 +883,12 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (DstTy == V6S16)
splitLoad(MI, {V4S16, V2S16}, V2S16);
else {
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("SplitLoad type not supported for MI");
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: SplitLoad, unsuported type",
+ MI);
+ return false;
}
- break;
+ return true;
}
case WidenLoad: {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
@@ -842,10 +899,12 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
else if (DstTy == V6S16)
widenLoad(MI, V8S16, V2S16);
else {
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("WidenLoad type not supported for MI");
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: WidenLoad, unsuported type",
+ MI);
+ return false;
}
- break;
+ return true;
}
case UnpackAExt:
return lowerUnpackAExt(MI);
@@ -855,8 +914,10 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
if (!WaterfallSgprs.empty()) {
MachineBasicBlock::iterator I = MI.getIterator();
- executeInWaterfallLoop(B, make_range(I, std::next(I)), WaterfallSgprs);
+ if (!executeInWaterfallLoop(B, make_range(I, std::next(I)), WaterfallSgprs))
+ return false;
}
+ return true;
}
LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
@@ -1055,7 +1116,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
}
}
-void RegBankLegalizeHelper::applyMappingDst(
+bool RegBankLegalizeHelper::applyMappingDst(
MachineInstr &MI, unsigned &OpIdx,
const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs) {
// Defs start from operand 0
@@ -1180,16 +1241,23 @@ void RegBankLegalizeHelper::applyMappingDst(
break;
}
case InvalidMapping: {
- LLVM_DEBUG(dbgs() << "Instruction with Invalid mapping: "; MI.dump(););
- llvm_unreachable("missing fast rule for MI");
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: missing fast rule ('Div' or 'Uni') for", MI);
+ return false;
}
default:
- llvm_unreachable("ID not supported");
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: applyMappingDst, ID not supported", MI);
+ return false;
}
}
+
+ return true;
}
-void RegBankLegalizeHelper::applyMappingSrc(
+bool RegBankLegalizeHelper::applyMappingSrc(
MachineInstr &MI, unsigned &OpIdx,
const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs,
SmallSet<Register, 4> &SgprWaterfallOperandRegs) {
@@ -1343,12 +1411,16 @@ void RegBankLegalizeHelper::applyMappingSrc(
break;
}
default:
- llvm_unreachable("ID not supported");
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: applyMappingSrc, ID not supported", MI);
+ return false;
}
}
+ return true;
}
-void RegBankLegalizeHelper::applyMappingPHI(MachineInstr &MI) {
+bool RegBankLegalizeHelper::applyMappingPHI(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
@@ -1371,16 +1443,17 @@ void RegBankLegalizeHelper::applyMappingPHI(MachineInstr &MI) {
MI.getOperand(i).setReg(NewUse.getReg(0));
}
- return;
+ return true;
}
- // ALL divergent i1 phis should be already lowered and inst-selected into PHI
- // with sgpr reg class and S1 LLT.
+ // ALL divergent i1 phis should have been lowered and inst-selected into PHI
+ // with sgpr reg class and S1 LLT in AMDGPUGlobalISelDivergenceLowering pass.
// Note: this includes divergent phis that don't require lowering.
if (Ty == LLT::scalar(1) && MUI.isDivergent(Dst)) {
- LLVM_DEBUG(dbgs() << "Divergent S1 G_PHI: "; MI.dump(););
- llvm_unreachable("Make sure to run AMDGPUGlobalISelDivergenceLowering "
- "before RegBankLegalize to lower lane mask(vcc) phis");
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: Can't lower divergent S1 G_PHI",
+ MI);
+ return false;
}
// We accept all types that can fit in some register class.
@@ -1388,11 +1461,13 @@ void RegBankLegalizeHelper::applyMappingPHI(MachineInstr &MI) {
// Divergent G_PHIs have vgpr dst but inputs can be sgpr or vgpr.
if (Ty == LLT::scalar(32) || Ty == LLT::pointer(1, 64) ||
Ty == LLT::pointer(4, 64)) {
- return;
+ return true;
}
- LLVM_DEBUG(dbgs() << "G_PHI not handled: "; MI.dump(););
- llvm_unreachable("type not supported");
+ reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: type not supported for G_PHI",
+ MI);
+ return false;
}
[[maybe_unused]] static bool verifyRegBankOnOperands(MachineInstr &MI,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
index 4f1c3c02fa5d6..1dc0278d6d90d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
@@ -12,6 +12,7 @@
#include "AMDGPURegBankLegalizeRules.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
namespace llvm {
@@ -27,11 +28,13 @@ namespace AMDGPU {
// to replace instruction. In other case InstApplyMethod will create new
// instruction(s).
class RegBankLegalizeHelper {
+ MachineFunction &MF;
const GCNSubtarget &ST;
MachineIRBuilder &B;
MachineRegisterInfo &MRI;
const MachineUniformityInfo &MUI;
const RegisterBankInfo &RBI;
+ MachineOptimizationRemarkEmitter MORE;
const RegBankLegalizeRules &RBLRules;
const bool IsWave32;
const RegisterBank *SgprRB;
@@ -81,10 +84,10 @@ class RegBankLegalizeHelper {
const RegisterBankInfo &RBI,
const RegBankLegalizeRules &RBLRules);
- void findRuleAndApplyMapping(MachineInstr &MI);
+ bool findRuleAndApplyMapping(MachineInstr &MI);
// Manual apply helpers.
- void applyMappingPHI(MachineInstr &MI);
+ bool applyMappingPHI(MachineInstr &MI);
void applyMappingTrivial(MachineInstr &MI);
private:
@@ -97,37 +100,37 @@ class RegBankLegalizeHelper {
const RegisterBank *getRegBankFromID(RegBankLLTMappingApplyID ID);
- void
+ bool
applyMappingDst(MachineInstr &MI, unsigned &OpIdx,
const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs);
- void
+ bool
applyMappingSrc(MachineInstr &MI, unsigned &OpIdx,
const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs,
SmallSet<Register, 4> &SgprWaterfallOperandRegs);
- void splitLoad(MachineInstr &MI, ArrayRef<LLT> LLTBreakdown,
+ bool splitLoad(MachineInstr &MI, ArrayRef<LLT> LLTBreakdown,
LLT MergeTy = LLT());
- void widenLoad(MachineInstr &MI, LLT WideTy, LLT MergeTy = LLT());
- void widenMMOToS32(GAnyLoad &MI) const;
+ bool widenLoad(MachineInstr &MI, LLT WideTy, LLT MergeTy = LLT());
+ bool widenMMOToS32(GAnyLoad &MI) const;
- void lower(MachineInstr &MI, const RegBankLLTMapping &Mapping,
+ bool lower(MachineInstr &MI, const RegBankLLTMapping &Mapping,
SmallSet<Register, 4> &SgprWaterfallOperandRegs);
- void lowerVccExtToSel(MachineInstr &MI);
+ bool lowerVccExtToSel(MachineInstr &MI);
std::pair<Register, Register> unpackZExt(Register Reg);
std::pair<Register, Register> unpackSExt(Register Reg);
std::pair<Register, Register> unpackAExt(Register Reg);
std::pair<Register, Register> unpackAExtTruncS16(Register Reg);
- void lowerUnpackBitShift(MachineInstr &MI);
- void lowerV_BFE(MachineInstr &MI);
- void lowerS_BFE(MachineInstr &MI);
- void lowerSplitTo32(MachineInstr &MI);
- void lowerSplitTo16(MachineInstr &MI);
- void lowerSplitTo32Select(MachineInstr &MI);
- void lowerSplitTo32SExtInReg(MachineInstr &MI);
- void lowerUnpackMinMax(MachineInstr &MI);
- void lowerUnpackAExt(MachineInstr &MI);
+ bool lowerUnpackBitShift(MachineInstr &MI);
+ bool lowerV_BFE(MachineInstr &MI);
+ bool lowerS_BFE(MachineInstr &MI);
+ bool lowerSplitTo32(MachineInstr &MI);
+ bool lowerSplitTo16(MachineInstr &MI);
+ bool lowerSplitTo32Select(MachineInstr &MI);
+ bool lowerSplitTo32SExtInReg(MachineInstr &MI);
+ bool lowerUnpackMinMax(MachineInstr &MI);
+ bool lowerUnpackAExt(MachineInstr &MI);
};
} // end namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 0c1daefd493b6..9de309279a247 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -243,7 +243,7 @@ UniformityLLTOpPredicateID LLTToBId(LLT Ty) {
return _;
}
-const RegBankLLTMapping &
+const RegBankLLTMapping *
SetOfRulesForOpcode::findMappingForMI(const MachineInstr &MI,
const MachineRegisterInfo &MRI,
const MachineUniformityInfo &MUI) const {
@@ -260,17 +260,16 @@ SetOfRulesForOpcode::findMappingForMI(const MachineInstr &MI,
Slot = getFastPredicateSlot(LLTToId(MRI.getType(Reg)));
if (Slot != -1)
- return MUI.isUniform(Reg) ? Uni[Slot] : Div[Slot];
+ return MUI.isUniform(Reg) ? &Uni[Slot] : &Div[Slot];
}
// Slow search for more complex rules.
for (const RegBankLegalizeRule &Rule : Rules) {
if (Rule.Predicate.match(MI, MUI, MRI))
- return Rule.OperandMapping;
+ return &Rule.OperandMapping;
}
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("None of the rules defined for MI's opcode matched MI");
+ return nullptr;
}
void SetOfRulesForOpcode::addRule(RegBankLegalizeRule Rule) {
@@ -353,7 +352,7 @@ RegBankLegalizeRules::addRulesForIOpcs(std::initializer_list<unsigned> OpcList,
return RuleSetInitializer(OpcList, IRulesAlias, IRules, FastTypes);
}
-const SetOfRulesForOpcode &
+const SetOfRulesForOpcode *
RegBankLegalizeRules::getRulesForOpc(MachineInstr &MI) const {
unsigned Opc = MI.getOpcode();
if (Opc == AMDGPU::G_INTRINSIC || Opc == AMDGPU::G_INTRINSIC_CONVERGENT ||
@@ -361,19 +360,15 @@ RegBankLegalizeRules::getRulesForOpc(MachineInstr &MI) const {
Opc == AMDGPU::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) {
unsigned IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
auto IRAIt = IRulesAlias.find(IntrID);
- if (IRAIt == IRulesAlias.end()) {
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("No rules defined for intrinsic opcode");
- }
- return IRules.at(IRAIt->second);
+ if (IRAIt == IRulesAlias.end())
+ return nullptr;
+ return &IRules.at(IRAIt->second);
}
auto GRAIt = GRulesAlias.find(Opc);
- if (GRAIt == GRulesAlias.end()) {
- LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
- llvm_unreachable("No rules defined for generic opcode");
- }
- return GRules.at(GRAIt->second);
+ if (GRAIt == GRulesAlias.end())
+ return nullptr;
+ return &GRules.at(GRAIt->second);
}
// Syntactic sugar wrapper for predicate lambda that enables '&&', '||' and '!'.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index 7e4ce7b43dc3b..1ac117304b76f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -287,7 +287,7 @@ class SetOfRulesForOpcode {
SetOfRulesForOpcode();
SetOfRulesForOpcode(FastRulesTypes FastTypes);
- const RegBankLLTMapping &
+ const RegBankLLTMapping *
findMappingForMI(const MachineInstr &MI, const MachineRegisterInfo &MRI,
const MachineUniformityInfo &MUI) const;
@@ -385,7 +385,7 @@ class RegBankLegalizeRules {
MRI = &_MRI;
};
- const SetOfRulesForOpcode &getRulesForOpc(MachineInstr &MI) const;
+ const SetOfRulesForOpcode *getRulesForOpc(MachineInstr &MI) const;
};
} // end namespace AMDGPU
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