[llvm] [AMDGPU] Fix AGPR_32 reg assign for mfma scale ops (PR #168964)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
index ddd119d8e..ffbb1c183 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
@@ -157,7 +157,8 @@ bool AMDGPURewriteAGPRCopyMFMAImpl::recomputeRegClassExceptRewritable(
       if (isRewriteCandidate(*MI)) {
         int AGPROp = AMDGPU::getMFMASrcCVDstAGPROp(MI->getOpcode());
         const MCInstrDesc &AGPRDesc = TII.get(AGPROp);
-        const TargetRegisterClass *NewRC = TII.getRegClass(AGPRDesc, MO.getOperandNo());
+        const TargetRegisterClass *NewRC =
+            TII.getRegClass(AGPRDesc, MO.getOperandNo());
         if (!TRI.hasAGPRs(NewRC))
           return false;
 

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https://github.com/llvm/llvm-project/pull/168964