[llvm] [AMDGPU] Fix AGPR_32 reg assign for mfma scale ops (PR #168964)

[Matt Arsenault via llvm-commits]

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@@ -152,9 +152,16 @@ bool AMDGPURewriteAGPRCopyMFMAImpl::recomputeRegClassExceptRewritable(
 
       // We can swap the classes of dst + src2 as a pair to AGPR, so ignore the
       // effects of rewrite candidates. It just so happens that we can use
-      // either AGPR or VGPR in src0/src1, so don't bother checking the
-      // constraint effects of the individual operands.
+      // either AGPR or VGPR in src0/src1. We still need to check constraint
+      // effects for scale variant, which does not allow AGPR.
       if (isRewriteCandidate(*MI)) {
+        unsigned OpNo = &MO - &MI->getOperand(0);
+        int AGPROp = AMDGPU::getMFMASrcCVDstAGPROp(MI->getOpcode());
+        const MCInstrDesc &AGPRDesc = TII.get(AGPROp);
+        const TargetRegisterClass *NewRC = TII.getRegClass(AGPRDesc, OpNo);
+        if (!NewRC || !TRI.hasAGPRs(NewRC))
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arsenm wrote:

```suggestion
        if (!TRI.hasAGPRs(NewRC))
```

No regclass cannot happen in this context 

https://github.com/llvm/llvm-project/pull/168964