[llvm] [llvm-exegesis] Add AArch64 operand initializers, SetRegTo (PR #169912)

[Simon Wallis via llvm-commits]

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@@ -80,6 +87,42 @@ loadFPCRImmediate(MCRegister Reg, unsigned RegBitWidth, const APInt &Value) {
   return {LoadImm, MoveToFPCR};
 }
 
+// Generates instructions to load an immediate value into a pair of W registers
+static std::vector<MCInst> loadWSeqPairImmediate(MCRegister Reg,
+                                                 unsigned RegBitWidth,
+                                                 const APInt &Value) {
+  MCRegister EvenReg = (Reg - AArch64::W0_W1) * 2 + AArch64::W0 + 0;
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simonwallis2 wrote:

There is prior art elsewhere in this file, in the handling of FPR8RegClass.
Yes I believe this use of MCRegister arithmetic is standard. It relies on members of the reg classes being contiguous. This is OK because they are contiguous.

https://github.com/llvm/llvm-project/pull/169912