[llvm] [AArch64][GISel] Add legalizer support for @llvm.umul.with.overflow.i128 (PR #170101)

[Matt Arsenault via llvm-commits]

================
@@ -7193,6 +7195,98 @@ LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
   return Legalized;
 }
 
+// Narrow unsigned multiplication with overflow (G_UMULO).
+LegalizerHelper::LegalizeResult
+LegalizerHelper::narrowScalarMULO(MachineInstr &MI, LLT NarrowTy) {
+  auto [DstReg, OverflowReg, Src1, Src2] = MI.getFirst4Regs();
+
+  LLT Ty = MRI.getType(DstReg);
+  if (Ty.isVector())
+    return UnableToLegalize;
+
+  unsigned Size = Ty.getSizeInBits();
+  unsigned NarrowSize = NarrowTy.getSizeInBits();
+  if (Size % NarrowSize != 0)
+    return UnableToLegalize;
+
+  unsigned NumParts = Size / NarrowSize;
+  if (NumParts != 2)
+    return UnableToLegalize; // Only handle i128→i64 narrowing
+
+  // Split inputs into high/low parts
+  SmallVector<Register, 2> Src1Parts, Src2Parts;
+  extractParts(Src1, NarrowTy, NumParts, Src1Parts, MIRBuilder, MRI);
+  extractParts(Src2, NarrowTy, NumParts, Src2Parts, MIRBuilder, MRI);
+
+  Register LHSLo = Src1Parts[0];
+  Register LHSHi = Src1Parts[1];
+  Register RHSLo = Src2Parts[0];
+  Register RHSHi = Src2Parts[1];
+
+  // Check if both high parts are non-zero → guaranteed overflow
+  Register Zero = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0);
----------------
arsenm wrote:

```suggestion
  auto Zero = MIRBuilder.buildConstant(NarrowTy, 0);
```

Generally this type of code stays in terms of the build results instead of adding a bunch of getReg() uses everywhere 

https://github.com/llvm/llvm-project/pull/170101