[llvm] [RISCV][llvm] Support PSLL codegen for P extension (PR #170074)

[Craig Topper via llvm-commits]

================
@@ -8592,6 +8593,39 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::VSELECT:
     return lowerToScalableOp(Op, DAG);
   case ISD::SHL:
+    if (Subtarget.enablePExtCodeGen() &&
+        Op.getSimpleValueType().isFixedLengthVector()) {
+      // There's no vector-vector version of shift instruction in P extension so
+      // we need to fallback to scalar computation and pack them back.
+      MVT VecVT = Op.getSimpleValueType();
+      unsigned NumElts = VecVT.getVectorNumElements();
+      MVT VecEltTy = VecVT.getVectorElementType();
+      SDValue Src0 = Op.getOperand(0);
+      SDValue Src1 = Op.getOperand(1);
+      SDLoc DL(Op);
+      SmallVector<SDValue, 2> Results;
+
+      // We have patterns for scalar/immediate shift amount, so no lowering
+      // needed.
+      if (Src1.getNode()->getOpcode() == ISD::SPLAT_VECTOR)
+        return Op;
+
+      for (unsigned I = 0; I < NumElts; ++I) {
----------------
topperc wrote:

Can we use DAG.UnrollVectorOp?

https://github.com/llvm/llvm-project/pull/170074