[llvm] 5c26015 - [AArch64][GlobalISel] Add GISel coverage for i32 lround and lrint. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 1 08:53:46 PST 2025
Author: David Green
Date: 2025-12-01T16:53:40Z
New Revision: 5c2601563789a232a9d0575c95edacdc2c25a97d
URL: https://github.com/llvm/llvm-project/commit/5c2601563789a232a9d0575c95edacdc2c25a97d
DIFF: https://github.com/llvm/llvm-project/commit/5c2601563789a232a9d0575c95edacdc2c25a97d.diff
LOG: [AArch64][GlobalISel] Add GISel coverage for i32 lround and lrint. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
llvm/test/CodeGen/AArch64/lrint-conv-win.ll
llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll
llvm/test/CodeGen/AArch64/lround-conv-win.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll b/llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
index ec9a8b2be8745..0fc8b9a9f57ad 100644
--- a/llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
+++ b/llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
@@ -1,36 +1,49 @@
-; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for testmhhs
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhws
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhxs
-; CHECK-LABEL: testmhhs:
-; CHECK: frintx h0, h0
-; CHECK-NEXT: fcvtzs w0, h0
-; CHECK-NEXT: ret
define i16 @testmhhs(half %x) {
+; CHECK-LABEL: testmhhs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs w0, s0
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
%conv = trunc i32 %0 to i16
ret i16 %conv
}
-; CHECK-LABEL: testmhws:
-; CHECK: frintx h0, h0
-; CHECK-NEXT: fcvtzs w0, h0
-; CHECK-NEXT: ret
define i32 @testmhws(half %x) {
+; CHECK-LABEL: testmhws:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs w0, s0
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}
-; CHECK-LABEL: testmhxs:
-; CHECK: frintx h0, h0
-; CHECK-NEXT: fcvtzs w8, h0
-; CHECK-NEXT: sxtw x0, w8
-; CHECK-NEXT: ret
define i64 @testmhxs(half %x) {
+; CHECK-LABEL: testmhxs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: sxtw x0, w8
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
-
-declare i32 @llvm.lrint.i32.f16(half) nounwind readnone
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/lrint-conv-win.ll b/llvm/test/CodeGen/AArch64/lrint-conv-win.ll
index 490f009c3fbab..164dbd854173c 100644
--- a/llvm/test/CodeGen/AArch64/lrint-conv-win.ll
+++ b/llvm/test/CodeGen/AArch64/lrint-conv-win.ll
@@ -1,48 +1,59 @@
-; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for testmsxs
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsws
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsxd
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmswd
-; CHECK-LABEL: testmsxs:
-; CHECK: frintx [[SREG:s[0-9]+]], s0
-; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
-; CHECK-NEXT: sxtw x0, [[WREG]]
-; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: sxtw x0, w8
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
-; CHECK-LABEL: testmsws:
-; CHECK: frintx [[SREG:s[0-9]+]], s0
-; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
-; CHECK-NEXT: ret
define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs w0, s0
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
ret i32 %0
}
-; CHECK-LABEL: testmsxd:
-; CHECK: frintx [[DREG:d[0-9]+]], d0
-; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
-; CHECK-NEXT: sxtw x0, [[WREG]]
-; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx d0, d0
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: sxtw x0, w8
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
-; CHECK-LABEL: testmswd:
-; CHECK: frintx [[DREG:d[0-9]+]], d0
-; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
-; CHECK-NEXT: ret
define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx d0, d0
+; CHECK-NEXT: fcvtzs w0, d0
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
ret i32 %0
}
-
-declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
-declare i32 @llvm.lrint.i32.f64(double) nounwind readnone
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll b/llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll
index 5eabc2a4f4630..e5390169c51d6 100644
--- a/llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll
+++ b/llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll
@@ -1,33 +1,62 @@
-; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-LABEL: testmhhs:
-; CHECK: fcvtas w0, h0
-; CHECK: ret
define i16 @testmhhs(half %x) {
+; CHECK-SD-LABEL: testmhhs:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvt s0, h0
+; CHECK-SD-NEXT: fcvtas w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testmhhs:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvt s0, h0
+; CHECK-GI-NEXT: fcvtas x0, s0
+; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-GI-NEXT: ret
entry:
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
%conv = trunc i32 %0 to i16
ret i16 %conv
}
-; CHECK-LABEL: testmhws:
-; CHECK: fcvtas w0, h0
-; CHECK: ret
define i32 @testmhws(half %x) {
+; CHECK-SD-LABEL: testmhws:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvt s0, h0
+; CHECK-SD-NEXT: fcvtas w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testmhws:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvt s0, h0
+; CHECK-GI-NEXT: fcvtas x0, s0
+; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-GI-NEXT: ret
entry:
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
ret i32 %0
}
-; CHECK-LABEL: testmhxs:
-; CHECK: fcvtas w8, h0
-; CHECK-NEXT: sxtw x0, w8
-; CHECK-NEXT: ret
define i64 @testmhxs(half %x) {
+; CHECK-SD-LABEL: testmhxs:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvt s0, h0
+; CHECK-SD-NEXT: fcvtas w8, s0
+; CHECK-SD-NEXT: sxtw x0, w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testmhxs:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvt s0, h0
+; CHECK-GI-NEXT: fcvtas x8, s0
+; CHECK-GI-NEXT: sxtw x0, w8
+; CHECK-GI-NEXT: ret
entry:
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
-
-declare i32 @llvm.lround.i32.f16(half) nounwind readnone
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/lround-conv-win.ll b/llvm/test/CodeGen/AArch64/lround-conv-win.ll
index 8bc9213fdcedf..02c1e9381eb06 100644
--- a/llvm/test/CodeGen/AArch64/lround-conv-win.ll
+++ b/llvm/test/CodeGen/AArch64/lround-conv-win.ll
@@ -1,44 +1,74 @@
-; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-LABEL: testmsxs:
-; CHECK: fcvtas w8, s0
-; CHECK-NEXT: sxtw x0, w8
-; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
+; CHECK-SD-LABEL: testmsxs:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtas w8, s0
+; CHECK-SD-NEXT: sxtw x0, w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testmsxs:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtas x8, s0
+; CHECK-GI-NEXT: sxtw x0, w8
+; CHECK-GI-NEXT: ret
entry:
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
-; CHECK-LABEL: testmsws:
-; CHECK: fcvtas w0, s0
-; CHECK-NEXT: ret
define i32 @testmsws(float %x) {
+; CHECK-SD-LABEL: testmsws:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtas w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testmsws:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtas x0, s0
+; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-GI-NEXT: ret
entry:
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
ret i32 %0
}
-; CHECK-LABEL: testmsxd:
-; CHECK: fcvtas w8, d0
-; CHECK-NEXT: sxtw x0, w8
-; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
+; CHECK-SD-LABEL: testmsxd:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtas w8, d0
+; CHECK-SD-NEXT: sxtw x0, w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testmsxd:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtas x8, d0
+; CHECK-GI-NEXT: sxtw x0, w8
+; CHECK-GI-NEXT: ret
entry:
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
-; CHECK-LABEL: testmswd:
-; CHECK: fcvtas w0, d0
-; CHECK-NEXT: ret
define i32 @testmswd(double %x) {
+; CHECK-SD-LABEL: testmswd:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtas w0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testmswd:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtas x0, d0
+; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-GI-NEXT: ret
entry:
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
ret i32 %0
}
-declare i32 @llvm.lround.i32.f32(float) nounwind readnone
-declare i32 @llvm.lround.i32.f64(double) nounwind readnone
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
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