[llvm] [AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes (PR #165546)

[via llvm-commits]

================
@@ -6805,6 +6805,83 @@ defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, ftrunc, "F
 defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fround, "FCVTAS">;
 defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fround, "FCVTAU">;
 
+// For global-isel we can use register classes to determine
+// which FCVT instruction to use.
+let Predicates = [HasFPRCVT] in {
----------------
Lukacma wrote:

Yes all the patterns without bitconvert node are for GlobalISel.  May I ask what would be the value in splitting the patch ? As there is only couple of GlobalISel patterns added and the tests can be shared anyway,  it makes sense to me to do it in one PR, but I can do that if you insist. The previous patches were also not split and it was fine.

https://github.com/llvm/llvm-project/pull/165546