[llvm] [SPIRV] Support for the extension SPV_INTEL_fpga_argument_interfaces (PR #140231)
Aadesh Premkumar via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 1 02:51:00 PST 2025
https://github.com/aadeshps-mcw updated https://github.com/llvm/llvm-project/pull/140231
>From 833d464a76eafa1b53739202b5ffad29a381da75 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Fri, 16 May 2025 15:33:11 +0530
Subject: [PATCH] --Added support for the extension
SPV_INTEL_fpga_argument_interfaces --Added test files for the extension
SPV_INTEL_fpga_argument_interfaces
---
llvm/docs/SPIRVUsage.rst | 3 +-
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 22 ++++++++--
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 4 +-
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 11 +++++
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 12 +++++-
.../sycl-kernel-arg-annotation.ll | 41 +++++++++++++++++++
6 files changed, 86 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 88164e6fa53d8..71eca44c79946 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -247,7 +247,8 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
- Adds new pipe read and write functions that have blocking semantics instead of the non-blocking semantics of the existing pipe read/write functions.
* - ``SPV_ALTERA_arbitrary_precision_fixed_point``
- Add instructions for fixed point arithmetic. The extension works without SPV_ALTERA_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
-
+ * - ``SPV_INTEL_fpga_argument_interfaces``
+ - Adds kernel argument decorations that influence the interfaces built for for Field Programmable Gate Array (FPGA) kernel arguments.
SPIR-V representation in LLVM IR
================================
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index dd57b74d79a5e..b929a291b0c39 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -314,6 +314,18 @@ getExecutionModel(const SPIRVSubtarget &STI, const Function &F) {
report_fatal_error("This HLSL entry point is not supported by this backend.");
}
+static bool shouldSkipOperands(SPIRV::Decoration::Decoration Dec) {
+ switch (Dec) {
+ case SPIRV::Decoration::StableKernelArgumentALTERA:
+ case SPIRV::Decoration::RegisterMapKernelArgumentALTERA:
+ case SPIRV::Decoration::ConduitKernelArgumentALTERA:
+ case SPIRV::Decoration::Restrict:
+ return true;
+ default:
+ return false;
+ }
+}
+
bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
ArrayRef<ArrayRef<Register>> VRegs,
@@ -406,10 +418,12 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
auto Dec =
static_cast<SPIRV::Decoration::Decoration>(Const->getZExtValue());
std::vector<uint32_t> DecVec;
- for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
- ConstantInt *Const = getConstInt(MD2, j);
- assert(Const && "MDOperand should be ConstantInt");
- DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
+ if (!shouldSkipOperands(Dec)) {
+ for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
+ ConstantInt *Const = getConstInt(MD2, j);
+ assert(Const && "MDOperand should be ConstantInt");
+ DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
+ }
}
buildOpDecorate(VRegs[i][0], MIRBuilder, Dec, DecVec);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 146384f4bf08c..76a7f5c83ae50 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -167,7 +167,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
{"SPV_ALTERA_arbitrary_precision_fixed_point",
SPIRV::Extension::Extension::
- SPV_ALTERA_arbitrary_precision_fixed_point}};
+ SPV_ALTERA_arbitrary_precision_fixed_point},
+ {"SPV_ALTERA_fpga_argument_interfaces",
+ SPIRV::Extension::Extension::SPV_ALTERA_fpga_argument_interfaces}};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 2feb73d8dedfa..7348f857e4bfd 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1002,6 +1002,17 @@ static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex,
Reqs.addRequirements(SPIRV::Capability::FloatControls2);
Reqs.addExtension(SPIRV::Extension::SPV_KHR_float_controls2);
}
+ } else if (Dec == SPIRV::Decoration::ConduitKernelArgumentALTERA ||
+ Dec == SPIRV::Decoration::RegisterMapKernelArgumentALTERA ||
+ Dec == SPIRV::Decoration::MMHostInterfaceAddressWidthALTERA ||
+ Dec == SPIRV::Decoration::MMHostInterfaceDataWidthALTERA ||
+ Dec == SPIRV::Decoration::MMHostInterfaceLatencyALTERA ||
+ Dec == SPIRV::Decoration::MMHostInterfaceReadWriteModeALTERA ||
+ Dec == SPIRV::Decoration::MMHostInterfaceMaxBurstALTERA ||
+ Dec == SPIRV::Decoration::MMHostInterfaceWaitRequestALTERA ||
+ Dec == SPIRV::Decoration::StableKernelArgumentALTERA) {
+ Reqs.addRequirements(SPIRV::Capability::FPGAArgumentInterfacesALTERA);
+ Reqs.addExtension(SPIRV::Extension::SPV_ALTERA_fpga_argument_interfaces);
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 94e0138c66487..018be0ad6c90f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -358,7 +358,7 @@ defm SPV_EXT_opacity_micromap : ExtensionOperand<98, [EnvVulkan]>;
defm SPV_NV_shader_invocation_reorder : ExtensionOperand<99, [EnvVulkan]>;
defm SPV_INTEL_usm_storage_classes : ExtensionOperand<100, [EnvOpenCL]>;
defm SPV_INTEL_fpga_latency_control : ExtensionOperand<101, [EnvOpenCL]>;
-defm SPV_INTEL_fpga_argument_interfaces : ExtensionOperand<102, [EnvOpenCL]>;
+defm SPV_ALTERA_fpga_argument_interfaces : ExtensionOperand<102, [EnvOpenCL]>;
defm SPV_INTEL_optnone : ExtensionOperand<103, [EnvOpenCL]>;
defm SPV_INTEL_function_pointers : ExtensionOperand<104, [EnvOpenCL]>;
defm SPV_INTEL_variable_length_array : ExtensionOperand<105, [EnvOpenCL]>;
@@ -617,6 +617,7 @@ defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [
defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>;
defm BlockingPipesALTERA : CapabilityOperand<5945, 0, 0, [SPV_ALTERA_blocking_pipes], []>;
defm ArbitraryPrecisionFixedPointALTERA : CapabilityOperand<5922, 0, 0, [SPV_ALTERA_arbitrary_precision_fixed_point], []>;
+defm FPGAArgumentInterfacesALTERA : CapabilityOperand<6174, 0, 0, [SPV_ALTERA_fpga_argument_interfaces], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
@@ -1403,6 +1404,15 @@ defm FunctionFloatingPointModeINTEL : DecorationOperand<6080, 0, 0, [], [Functio
defm AliasScopeINTEL : DecorationOperand<5914, 0, 0, [], [MemoryAccessAliasingINTEL]>;
defm NoAliasINTEL : DecorationOperand<5915, 0, 0, [], [MemoryAccessAliasingINTEL]>;
defm FPMaxErrorDecorationINTEL : DecorationOperand<6170, 0, 0, [], [FPMaxErrorINTEL]>;
+defm ConduitKernelArgumentALTERA: DecorationOperand<6175, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
+defm RegisterMapKernelArgumentALTERA: DecorationOperand<6176, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
+defm MMHostInterfaceAddressWidthALTERA: DecorationOperand<6177, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
+defm MMHostInterfaceDataWidthALTERA: DecorationOperand<6178, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
+defm MMHostInterfaceLatencyALTERA: DecorationOperand<6179, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
+defm MMHostInterfaceReadWriteModeALTERA: DecorationOperand<6180, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
+defm MMHostInterfaceMaxBurstALTERA: DecorationOperand<6181, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
+defm MMHostInterfaceWaitRequestALTERA: DecorationOperand<6182, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
+defm StableKernelArgumentALTERA: DecorationOperand<6183, 0, 0, [], [FPGAArgumentInterfacesALTERA]>;
//===----------------------------------------------------------------------===//
// Multiclass used to define BuiltIn enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll
new file mode 100644
index 0000000000000..0ec9d59f8c502
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll
@@ -0,0 +1,41 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_ALTERA_fpga_argument_interfaces %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; CHECK: OpCapability FPGAArgumentInterfacesALTERA
+; CHECK: OpExtension "SPV_ALTERA_fpga_argument_interfaces"
+; CHECK: OpName %[[ID:[0-9]+]] "_arg_p"
+; CHECK: OpDecorate %[[ID]] Alignment 4
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceAddressWidthALTERA 32
+; CHECK: OpDecorate %[[ID]] ConduitKernelArgumentALTERA
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceDataWidthALTERA 64
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceLatencyALTERA 1
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceMaxBurstALTERA 3
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceReadWriteModeALTERA 2
+; CHECK: OpDecorate %[[ID]] RegisterMapKernelArgumentALTERA
+; CHECK: OpDecorate %[[ID]] StableKernelArgumentALTERA
+; CHECK: OpDecorate %[[ID]] Restrict
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceWaitRequestALTERA 5
+
+$_ZTS4MyIP = comdat any
+
+define weak_odr dso_local spir_kernel void @_ZTS4MyIP(ptr addrspace(4) noundef %_arg_p) #0 comdat !spirv.ParameterDecorations !1588
+; CHECK-LLVM-DAG: !spirv.ParameterDecorations ![[PARMDECOR:[0-9]+]]
+{
+entry:
+ ret void
+}
+
+!1587 = !{i32 -1}
+!1588 = !{!1589}
+!1589 = !{!1590, !1591, !1593, !1594, !1595, !1596, !1597, !1598, !1599, !1600, !1601}
+!1590 = !{i32 44, i32 4}
+!1591 = !{i32 6177, i32 32}
+!1593 = !{i32 6175, i32 1}
+!1594 = !{i32 6178, i32 64}
+!1595 = !{i32 6179, i32 1}
+!1596 = !{i32 6181, i32 3}
+!1597 = !{i32 6180, i32 2}
+!1598 = !{i32 6176, i32 1}
+!1599 = !{i32 6183, i32 1}
+!1600 = !{i32 19, i32 1}
+!1601 = !{i32 6182, i32 5}
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