[llvm] [LLVM][CodeGen][SVE] Add lowering for ISD::[ANY,SIGN,ZERO]_EXTEND_VECTOR_INREG. (PR #169847)

[Paul Walker via llvm-commits]

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@@ -1591,6 +1591,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::AVGCEILS, VT, Custom);
       setOperationAction(ISD::AVGCEILU, VT, Custom);
 
+      setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Custom);
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paulwalker-arm wrote:

For `###_EXTEND_VECTOR_INREG` the result type is used.  The operations require both types to be the same size so it would be `nxv2i64 -> nxv1i128`, which is not a legal type so the current lowering code wouldn't apply.

I'm pretty sure that means this case will fail, but that's no worse than today.

https://github.com/llvm/llvm-project/pull/169847