[llvm] [AArch64] Improve select dagcombine (PR #169925)

[Sander de Smalen via llvm-commits]

================
@@ -26965,6 +26965,10 @@ static SDValue performSelectCombine(SDNode *N,
   if (!ResVT.isVector() || NumMaskElts == 0)
     return SDValue();
 
+  // Avoid creating vectors with excessive VFs before legalization.
+  if (DCI.isBeforeLegalize())
+    NumMaskElts = ResVT.getVectorNumElements();
----------------
sdesmalen-arm wrote:

Below it bails out in case `CCVT.getSizeInBits() != ResVT.getSizeInBits()`, we may just as well bail out here rather than setting `NumMaskElts` to a different value, i.e.

```
if (DCI.isBeforeLegalize() && NumMaskElts != ResVT.getVectorNumElements())
  return SDValue();
```


https://github.com/llvm/llvm-project/pull/169925