[llvm] [SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) (PR #170076)

[Simon Pilgrim via llvm-commits]

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@@ -10867,6 +10867,16 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
   assert(VT == RHS.getValueType() && "Expected operands to be the same type");
   assert(VT.isInteger() && "Expected operands to be integers");
 
+  // usub.sat(a, 1) -> a - zext(a != 0)
+  if (Opcode == ISD::USUBSAT && !VT.isVector() && isOneConstant(RHS)) {
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RKSimon wrote:

Why no vector support?

https://github.com/llvm/llvm-project/pull/170076