[llvm] [M68k] add test showing callseq begin failure for doubles, and fix mem chain generation (PR #170049)

[via llvm-commits]

https://github.com/knickish updated https://github.com/llvm/llvm-project/pull/170049

>From 5b87c122803ceb5d8cb773891b168a8bee630855 Mon Sep 17 00:00:00 2001
From: kirk <knickish at gmail.com>
Date: Sun, 23 Mar 2025 01:05:12 +0000
Subject: [PATCH] [M68k] add test showing callseq begin failure for doubles,
 and fix mem chain generation

---
 .../SelectionDAG/ScheduleDAGRRList.cpp        |  6 ++-
 llvm/lib/Target/M68k/M68kISelLowering.cpp     |  7 +--
 llvm/test/CodeGen/M68k/Regression/146213.ll   | 54 +++++++++++++++++++
 3 files changed, 59 insertions(+), 8 deletions(-)
 create mode 100644 llvm/test/CodeGen/M68k/Regression/146213.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 12fc26d949581..09f7e07fb0343 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -507,7 +507,8 @@ FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
             BestMaxNest = MyMaxNest;
           }
       }
-      assert(Best);
+      if (!Best)
+        return nullptr;
       MaxNest = BestMaxNest;
       return Best;
     }
@@ -584,7 +585,8 @@ void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
         unsigned NestLevel = 0;
         unsigned MaxNest = 0;
         SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
-        assert(N && "Must find call sequence start");
+        if (!N)
+          break;
 
         SUnit *Def = &SUnits[N->getNodeId()];
         CallSeqEndForStart[Def] = SU;
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 65084087f6e3f..c1810b0067478 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -633,7 +633,6 @@ SDValue M68kTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
     Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff, DL);
 
   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
-  SmallVector<SDValue, 8> MemOpChains;
   SDValue StackPtr;
 
   // Walk the register/memloc assignments, inserting copies/loads.  In the case
@@ -689,14 +688,10 @@ SDValue M68kTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
         StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
                                       getPointerTy(DAG.getDataLayout()));
       }
-      MemOpChains.push_back(
-          LowerMemOpCallTo(Chain, StackPtr, Arg, DL, DAG, VA, Flags));
+      Chain = LowerMemOpCallTo(Chain, StackPtr, Arg, DL, DAG, VA, Flags);
     }
   }
 
-  if (!MemOpChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
-
   // FIXME Make sure PIC style GOT works as expected
   // The only time GOT is really needed is for Medium-PIC static data
   // otherwise we are happy with pc-rel or static references
diff --git a/llvm/test/CodeGen/M68k/Regression/146213.ll b/llvm/test/CodeGen/M68k/Regression/146213.ll
new file mode 100644
index 0000000000000..997df1b569ca7
--- /dev/null
+++ b/llvm/test/CodeGen/M68k/Regression/146213.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=m68k-linux | FileCheck %s
+
+declare float @float_arg(float)
+declare float @double_arg(double)
+
+define float @float_arg_test(ptr %inout) nounwind {
+; CHECK-LABEL: float_arg_test:
+; CHECK:       ; %bb.0: ; %start
+; CHECK-NEXT:    suba.l #12, %sp
+; CHECK-NEXT:    movem.l %a2, (8,%sp) ; 8-byte Folded Spill
+; CHECK-NEXT:    move.l #0, (%sp)
+; CHECK-NEXT:    jsr float_arg
+; CHECK-NEXT:    move.l (16,%sp), %a2
+; CHECK-NEXT:    move.l (%a2), (%sp)
+; CHECK-NEXT:    move.l #0, (4,%sp)
+; CHECK-NEXT:    jsr __mulsf3
+; CHECK-NEXT:    move.l %d0, (%a2)
+; CHECK-NEXT:    moveq #0, %d0
+; CHECK-NEXT:    movem.l (8,%sp), %a2 ; 8-byte Folded Reload
+; CHECK-NEXT:    adda.l #12, %sp
+; CHECK-NEXT:    rts
+start:
+  %_58 = call float @float_arg(float 0.000000e+00)
+  %_60 = load float, ptr %inout, align 8
+  %_57 = fmul float 0.000000e+00, %_60
+  store float %_57, ptr %inout, align 8
+  ret float 0.000000e+00
+}
+
+define float @double_arg_test(ptr %inout) nounwind {
+; CHECK-LABEL: double_arg_test:
+; CHECK:       ; %bb.0: ; %start
+; CHECK-NEXT:    suba.l #12, %sp
+; CHECK-NEXT:    movem.l %a2, (8,%sp) ; 8-byte Folded Spill
+; CHECK-NEXT:    move.l #0, (4,%sp)
+; CHECK-NEXT:    move.l #0, (%sp)
+; CHECK-NEXT:    jsr double_arg
+; CHECK-NEXT:    move.l (16,%sp), %a2
+; CHECK-NEXT:    move.l (%a2), (%sp)
+; CHECK-NEXT:    move.l #0, (4,%sp)
+; CHECK-NEXT:    jsr __mulsf3
+; CHECK-NEXT:    move.l %d0, (%a2)
+; CHECK-NEXT:    moveq #0, %d0
+; CHECK-NEXT:    movem.l (8,%sp), %a2 ; 8-byte Folded Reload
+; CHECK-NEXT:    adda.l #12, %sp
+; CHECK-NEXT:    rts
+start:
+  %_58 = call float @double_arg(double 0.000000e+00)
+  %_60 = load float, ptr %inout, align 8
+  %_57 = fmul float 0.000000e+00, %_60
+  store float %_57, ptr %inout, align 8
+  ret float 0.000000e+00
+}