[llvm] [AArch64] Combine vector FNEG+FMA into `FNML[A|S]` (PR #167900)

[Sander de Smalen via llvm-commits]

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@@ -43,10 +48,11 @@ define <8 x double> @simple_symmetric_muladd4(<8 x double> %a, <8 x double> %b)
 ; CHECK-NEXT:    zip1 v17.2d, v5.2d, v7.2d
 ; CHECK-NEXT:    zip2 v5.2d, v5.2d, v7.2d
 ; CHECK-NEXT:    dup v6.2d, x8
-; CHECK-NEXT:    fmla v3.2d, v6.2d, v16.2d
-; CHECK-NEXT:    fmla v4.2d, v6.2d, v0.2d
-; CHECK-NEXT:    fmla v17.2d, v6.2d, v2.2d
-; CHECK-NEXT:    fmla v5.2d, v6.2d, v1.2d
+; CHECK-NEXT:    ptrue p0.d, vl2
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sdesmalen-arm wrote:

This (the extra ptrue) is an unnecessary side-effect and was also the reason that I hadn't yet enabled this for plain FMAs after landing #166926.

If you implement this as a DAGCombine after type legalization to map these operations to a `fnmls_p` or `fnmla_p` node (those don't exist yet, but you can add them to AArch64SVEInstrInfo.td (see e.g. `def AArch64fma_p`)) and then add them to the corresponding PatFrags (e.g. `AArch64fnmls_p` and `AArch64fnmla_p`), then it would only happen for the case where we know this will reduce instructions.

https://github.com/llvm/llvm-project/pull/167900