[llvm] [AArch64] Combine vector FNEG+FMA into `FNML[A|S]` (PR #167900)

[Sander de Smalen via llvm-commits]

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@@ -7730,6 +7734,37 @@ SDValue AArch64TargetLowering::LowerFMUL(SDValue Op, SelectionDAG &DAG) const {
   return FCVTNT(VT, BottomBF16, Pg, TopF32);
 }
 
+SDValue AArch64TargetLowering::LowerFMA(SDValue Op, SelectionDAG &DAG) const {
+  SDValue OpA = Op->getOperand(0);
+  SDValue OpB = Op->getOperand(1);
+  SDValue OpC = Op->getOperand(2);
+  EVT VT = Op.getValueType();
+  SDLoc DL(Op);
+
+  // Bail early if we're definitely not looking to merge FNEGs into the FMA.
+  if (!VT.isFixedLengthVector() || OpC.getOpcode() != ISD::FNEG) {
+    return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED);
+  }
+
+  // Convert FMA/FNEG nodes to SVE to enable the following patterns:
+  // fma(a, b, neg(c)) -> fnmls(a, b, c)
+  // fma(neg(a), b, neg(c)) -> fnmla(a, b, c)
+  // fma(a, neg(b), neg(c)) -> fnmla(a, b, c)
+  SDValue Pg = getPredicateForVector(DAG, DL, VT);
+  EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
+
+  for (SDValue *Op : {&OpA, &OpB, &OpC}) {
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sdesmalen-arm wrote:

You can remove `OpC` from this list and the ternary operation below (`Op->getOpcode() == ISD::FNEG ? .. : ..`) because we know OpC is a `FNEG`. Then there would little value be left in having the loop for the other two operands.

https://github.com/llvm/llvm-project/pull/167900