[llvm] [AArch64] Combine vector FNEG+FMA into `FNML[A|S]` (PR #167900)

[Benjamin Maxwell via llvm-commits]

================
@@ -7732,6 +7734,37 @@ SDValue AArch64TargetLowering::LowerFMUL(SDValue Op, SelectionDAG &DAG) const {
   return FCVTNT(VT, BottomBF16, Pg, TopF32);
 }
 
+SDValue AArch64TargetLowering::LowerFMA(SDValue Op, SelectionDAG &DAG) const {
+  SDValue OpA = Op->getOperand(0);
+  SDValue OpB = Op->getOperand(1);
+  SDValue OpC = Op->getOperand(2);
+  EVT VT = Op.getValueType();
+  SDLoc DL(Op);
+
+  // Bail early if we're definitely not looking to merge FNEGs into the FMA.
+  if (!VT.isFixedLengthVector() || OpC.getOpcode() != ISD::FNEG) {
+    return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED);
+  }
----------------
MacDue wrote:

It's a little awkward, but you can do:
```suggestion
  // Bail early if we're definitely not looking to merge FNEGs into the FMA.
  if (!VT.isFixedLengthVector() || OpC.getOpcode() != ISD::FNEG)
    if (VT.isScalableVector() || VT.getScalarType() == MVT::bf16 ||
        useSVEForFixedLengthVectorVT(VT, !Subtarget->isNeonAvailable()))
      return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED);
    return Op; // Fallback to NEON lowering.
  }
```
To avoid promoting FMAs that don't match the pattern to SVE.

https://github.com/llvm/llvm-project/pull/167900