[llvm] [X86] Add ISD::MULHS/MULHU v4i64/v8i64 lowering (PR #169819)

[Phoebe Wang via llvm-commits]

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@@ -622,90 +622,85 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
 ;
 ; AVX2-LABEL: dont_fold_srem_i64:
 ; AVX2:       # %bb.0:
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phoebewang wrote:

The change doesn't look a win to me, even include AVX512. I have 2 concerns: 1) vector operations consume more power, especially the mul operation. It may cause frequency drop on some targets; 2) the new code consume more registers, the problem is serious if FP/vector registers are heavily used, and there're functions calls since they are caller save registers.

Maybe collect some micro-benchmark data on real machines?

https://github.com/llvm/llvm-project/pull/169819