[llvm] [AArch64] Use umin for x != 0 when +cssc is enabled (PR #169159)

[Benjamin Maxwell via llvm-commits]

================
@@ -26417,6 +26418,12 @@ static SDValue performSETCCCombine(SDNode *N,
       return DAG.getNode(ISD::SETCC, DL, VT, TST, RHS, N->getOperand(2));
     }
   }
+  if (Subtarget->hasCSSC() && Cond == ISD::SETNE && isNullConstant(RHS) &&
+      !VT.isVector() && DCI.getDAGCombineLevel() >= AfterLegalizeTypes) {
+    SDValue One = DAG.getConstant(1, DL, LHS.getValueType());
+    auto UMin = DAG.getNode(ISD::UMIN, DL, LHS.getValueType(), LHS, One);
+    return DAG.getNode(ISD::TRUNCATE, DL, VT, UMin);
+  }
----------------
MacDue wrote:

Could you move this to `AArch64TargetLowering::LowerSETCC`? Under `if (LHS.getValueType().isInteger())`:
```c++
    if (Subtarget->hasCSSC() && CC == ISD::SETNE && isNullConstant(RHS)) {
      SDValue One = DAG.getConstant(1, DL, LHS.getValueType());
      auto UMin = DAG.getNode(ISD::UMIN, DL, LHS.getValueType(), LHS, One);
      SDValue Res = DAG.getNode(ISD::TRUNCATE, DL, VT, UMin);
      return IsStrict ? DAG.getMergeValues({Res, Chain}, DL) : Res;
    }
```
It does not change any of your tests, but it seems like a better place (as until we lower this `setcc` is more canonical).

https://github.com/llvm/llvm-project/pull/169159