[llvm] [AArch64] Mark FMOVvXfY_ns as rematerializable, cheap (PR #169186)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Guy David (guy-david)

<details>
<summary>Changes</summary>

Otherwise, the register allocator may spill and reload constants that can be rematerialized with a single instruction.
This concerns instructions such as `fmov.4s v0, #<!-- -->1.00000000` or `fmov.2d v0, #<!-- -->0.25000000`.

---
Full diff: https://github.com/llvm/llvm-project/pull/169186.diff


1 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+2) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 50a3a4ab8d8b6..8dca6a054aa52 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -8354,6 +8354,7 @@ def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
 }
 
 // AdvSIMD FMOV
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,
                                               "fmov", ".2d",
                        [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
@@ -8371,6 +8372,7 @@ def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8,
                                               "fmov", ".8h",
                        [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
 } // Predicates = [HasNEON, HasFullFP16]
+}
 
 // AdvSIMD MOVI
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/169186