[llvm] [AArch64] Mark FMOVvXfY_ns as rematerializable, cheap (PR #169186)
Guy David via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 22 12:42:56 PST 2025
https://github.com/guy-david created https://github.com/llvm/llvm-project/pull/169186
Otherwise, the register allocator may spill and reload constants that can be rematerialized with a single instruction.
This concerns instructions such as `fmov.4s v0, #1.00000000` or `fmov.2d v0, #0.25000000`.
>From bac88b56a18a8dbd15bb1a8c230be668f6c70df7 Mon Sep 17 00:00:00 2001
From: Guy David <guyda96 at gmail.com>
Date: Sat, 22 Nov 2025 19:45:46 +0200
Subject: [PATCH] [AArch64] Mark FMOVvXfY_ns as rematerializable, cheap
Otherwise, the register allocator may spill and reload constants that
can be rematerialized with a single instruction.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 50a3a4ab8d8b6..8dca6a054aa52 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -8354,6 +8354,7 @@ def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
}
// AdvSIMD FMOV
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,
"fmov", ".2d",
[(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
@@ -8371,6 +8372,7 @@ def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8,
"fmov", ".8h",
[(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
} // Predicates = [HasNEON, HasFullFP16]
+}
// AdvSIMD MOVI
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