[llvm] Use umin for x != 0 when +cssc is enabled (PR #169159)

[via llvm-commits]

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@@ -26417,6 +26418,11 @@ static SDValue performSETCCCombine(SDNode *N,
       return DAG.getNode(ISD::SETCC, DL, VT, TST, RHS, N->getOperand(2));
     }
   }
+  if (Subtarget->hasCSSC() && Cond == ISD::SETNE && isNullConstant(RHS)) {
+    SDValue One = DAG.getConstant(1, DL, LHS.getValueType());
+    auto UMin = DAG.getNode(ISD::UMIN, DL, LHS.getValueType(), LHS, One);
+    return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, UMin);
+  }
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clingfei wrote:

In my new commit, I changed `MVT::i1` to the VT of `SETCC`.

However, I only see `SETCC` of type `i1` (even though the return value is a wider integer type) or a vector type.
For the latter, I think `isNullConstant(RHS)` should always return false.

https://github.com/llvm/llvm-project/pull/169159