[llvm] Use umin for x != 0 when +cssc is enabled (PR #169159)

[Benjamin Maxwell via llvm-commits]

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@@ -26417,6 +26418,11 @@ static SDValue performSETCCCombine(SDNode *N,
       return DAG.getNode(ISD::SETCC, DL, VT, TST, RHS, N->getOperand(2));
     }
   }
+  if (Subtarget->hasCSSC() && Cond == ISD::SETNE && isNullConstant(RHS)) {
+    SDValue One = DAG.getConstant(1, DL, LHS.getValueType());
+    auto UMin = DAG.getNode(ISD::UMIN, DL, LHS.getValueType(), LHS, One);
+    return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, UMin);
+  }
----------------
MacDue wrote:

Can you add a test like:
```
define <4 x i1> @icmpv4i32(<4 x i32> %0) {
entry:
  %2 = icmp ne <4 x i32> %0, 0
  ret <4 x i1> %2
}
```
To show what happens for vector types? Generally, I'd much prefer explicit type checks, as they make the intent of the pattern more obvious and less likely to result in bugs down the line.

https://github.com/llvm/llvm-project/pull/169159