[llvm] [RISCV] Implement RVV scheduling model for andes 45 series processor. (PR #167821)

[Min-Yih Hsu via llvm-commits]

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mshockwave wrote:

FWIW, SpacemitX60 also has this property. But I agree it'd be nice to double check if this is true or not (not necessarily has to be in this patch though)

https://github.com/llvm/llvm-project/pull/167821