[llvm] [RISCV] Implement RVV scheduling model for andes 45 series processor. (PR #167821)
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 16 16:44:48 PST 2025
https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/167821
>From 4c766e7c87e6154afeb15dd31d547bcaa261e2e7 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 25 Jun 2025 16:18:39 +0800
Subject: [PATCH 1/2] [RISCV] Implement RVV scheduling model for andes 45
series processor.
This patch implements RVV scheduling model for andes45 series
processors.
Some of scheduling categories are left with a TODO mark. We will revise
its latency and throughput in the future.
---
llvm/lib/Target/RISCV/RISCVSchedAndes45.td | 1095 ++-
llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s | 40 +-
llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s | 98 +-
.../llvm-mca/RISCV/Andes45/rvv-arithmetic.s | 6838 +++++++++++++++++
.../llvm-mca/RISCV/Andes45/rvv-bitwise.s | 4346 +++++++++++
.../llvm-mca/RISCV/Andes45/rvv-comparison.s | 2722 +++++++
.../llvm-mca/RISCV/Andes45/rvv-conversion.s | 1775 +++++
.../tools/llvm-mca/RISCV/Andes45/rvv-fma.s | 2203 ++++++
.../tools/llvm-mca/RISCV/Andes45/rvv-fp.s | 5617 ++++++++++++++
.../tools/llvm-mca/RISCV/Andes45/rvv-mask.s | 1882 +++++
.../tools/llvm-mca/RISCV/Andes45/rvv-minmax.s | 1126 +++
.../llvm-mca/RISCV/Andes45/rvv-mul-div.s | 3002 ++++++++
.../llvm-mca/RISCV/Andes45/rvv-permutation.s | 3522 +++++++++
.../llvm-mca/RISCV/Andes45/rvv-reduction.s | 1842 +++++
.../llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s | 558 ++
.../llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s | 332 +
.../llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s | 4743 ++++++++++++
.../llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s | 604 ++
18 files changed, 42282 insertions(+), 63 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mask.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index 8cf15fa26e22d..207a240e5c896 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -8,7 +8,238 @@
//===----------------------------------------------------------------------===//
-// FIXME: Implement sheduling model for V and other extensions.
+// Refer to `Table 5: Supported VLEN and DLEN` for legal VLEN and DLEN.
+defvar Andes45VLEN = 512;
+defvar Andes45DLEN = 512;
+defvar Andes45VLEN_DLEN_RATIO = !div(Andes45VLEN, Andes45DLEN);
+
+assert !or(!eq(Andes45VLEN_DLEN_RATIO, 1), !eq(Andes45VLEN_DLEN_RATIO, 2)),
+ "Andes45VLEN / Andes45DLEN should be 1 or 2";
+
+// Refer to `Table 6: Supported DLEN and BIU_DATA_WIDTH` for legal BIU_DATA_WIDTH.
+defvar Andes45BIU_DATA_WIDTH = 512;
+defvar Andes45DLEN_BIU_DATA_WIDTH_RATIO = !div(Andes45DLEN, Andes45BIU_DATA_WIDTH);
+
+assert !or(!eq(Andes45DLEN_BIU_DATA_WIDTH_RATIO, 1), !eq(Andes45DLEN_BIU_DATA_WIDTH_RATIO, 2)),
+ "Andes45DLEN / Andes45DLEN_BIU_DATA_WIDTH_RATIO should be 1 or 2";
+
+// HVM region: VLSU_MEM_DW equals DLEN
+// Cachable/Non-cachable region: VLSU_MEM_DW equals BIU_DATA_WIDTH
+defvar Andes45VLSU_MEM_DW = Andes45BIU_DATA_WIDTH;
+defvar Andes45VLEN_VLSU_MEM_DW_RATIO = !div(Andes45VLEN, Andes45VLSU_MEM_DW);
+
+// There are various latency depending on its memory type and status.
+defvar VLSU_MEM_LATENCY = 13;
+
+// The worst case LMUL is the largest LMUL.
+class Andes45IsWorstCaseMX<string mx, list<string> MxList> {
+ defvar LLMUL = LargestLMUL<MxList>.r;
+ bit c = !eq(mx, LLMUL);
+}
+
+// The worst case is the largest LMUL with the smallest SEW.
+class Andes45IsWorstCaseMXSEW<string mx, int sew, list<string> MxList,
+ bit isF = 0> {
+ defvar LLMUL = LargestLMUL<MxList>.r;
+ defvar SSEW = SmallestSEW<mx, isF>.r;
+ bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+// When fractional LMUL is used, the LMUL used in calculation is 1.
+class Andes45GetLMULValue<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 1,
+ !eq(mx, "M2") : 2,
+ !eq(mx, "M4") : 4,
+ !eq(mx, "M8") : 8,
+ !eq(mx, "MF2") : 1,
+ !eq(mx, "MF4") : 1,
+ !eq(mx, "MF8") : 1
+ );
+}
+
+// (VLEN/DLEN)*LMUL
+// When fractional LMUL is used, the LMUL used in calculation is 1.
+class Andes45GetCyclesDefault<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : !mul(Andes45VLEN_DLEN_RATIO, 1),
+ !eq(mx, "M2") : !mul(Andes45VLEN_DLEN_RATIO, 2),
+ !eq(mx, "M4") : !mul(Andes45VLEN_DLEN_RATIO, 4),
+ !eq(mx, "M8") : !mul(Andes45VLEN_DLEN_RATIO, 8),
+ !eq(mx, "MF2") : !mul(Andes45VLEN_DLEN_RATIO, 1),
+ !eq(mx, "MF4") : !mul(Andes45VLEN_DLEN_RATIO, 1),
+ !eq(mx, "MF8") : !mul(Andes45VLEN_DLEN_RATIO, 1)
+ );
+}
+
+// (VLEN/DLEN)*LMUL*2, if LMUL >= 1,
+// (VLEN != DLEN) ? : 4 : 1, if LMUL < 1.
+class Andes45GetCyclesWidening<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : !mul(Andes45VLEN_DLEN_RATIO, 2),
+ !eq(mx, "M2") : !mul(Andes45VLEN_DLEN_RATIO, 4),
+ !eq(mx, "M4") : !mul(Andes45VLEN_DLEN_RATIO, 8),
+ // FIXME: .v* and .w* are different if LMUL < 1.
+ !eq(mx, "MF2") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1),
+ !eq(mx, "MF4") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1),
+ !eq(mx, "MF8") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1),
+ );
+}
+
+// (VLEN/DLEN)*LMUL*2, if LMUL >= 1,
+// (VLEN != DLEN) ? : 4 : 1, if LMUL < 1.
+class Andes45GetCyclesNarrowing<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : !mul(Andes45VLEN_DLEN_RATIO, 2),
+ !eq(mx, "M2") : !mul(Andes45VLEN_DLEN_RATIO, 4),
+ !eq(mx, "M4") : !mul(Andes45VLEN_DLEN_RATIO, 8),
+ !eq(mx, "MF2") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1),
+ !eq(mx, "MF4") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1),
+ !eq(mx, "MF8") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1)
+ );
+}
+
+// 3, if LMUL >= 1,
+// (VLEN != DLEN) ? 3 : 2, if LMUL <1.
+class Andes45GetLatencyNarrowing<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 3,
+ !eq(mx, "M2") : 3,
+ !eq(mx, "M4") : 3,
+ !eq(mx, "MF2") : !if(!ne(Andes45VLEN, Andes45DLEN), 3, 2),
+ !eq(mx, "MF4") : !if(!ne(Andes45VLEN, Andes45DLEN), 3, 2),
+ !eq(mx, "MF8") : !if(!ne(Andes45VLEN, Andes45DLEN), 3, 2)
+ );
+}
+
+// (VLEN/VLSU_MEM_DW)*EMUL
+class Andes45GetCyclesLoadStore<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : !mul(Andes45VLEN_VLSU_MEM_DW_RATIO, 1),
+ !eq(mx, "M2") : !mul(Andes45VLEN_VLSU_MEM_DW_RATIO, 2),
+ !eq(mx, "M4") : !mul(Andes45VLEN_VLSU_MEM_DW_RATIO, 4),
+ !eq(mx, "M8") : !mul(Andes45VLEN_VLSU_MEM_DW_RATIO, 8),
+ !eq(mx, "MF2") : !mul(Andes45VLEN_VLSU_MEM_DW_RATIO, 1),
+ !eq(mx, "MF4") : !mul(Andes45VLEN_VLSU_MEM_DW_RATIO, 1),
+ !eq(mx, "MF8") : !mul(Andes45VLEN_VLSU_MEM_DW_RATIO, 1)
+ );
+}
+
+class Andes45GetCyclesOnePerElement<string mx, int sew> {
+ int VL = !div(Andes45VLEN, sew);
+ int c = !cond(
+ !eq(mx, "M1") : VL,
+ !eq(mx, "M2") : !mul(VL, 2),
+ !eq(mx, "M4") : !mul(VL, 4),
+ !eq(mx, "M8") : !mul(VL, 8),
+ !eq(mx, "MF2") : !div(VL, 2),
+ !eq(mx, "MF4") : !div(VL, 4),
+ !eq(mx, "MF8") : !div(VL, 8)
+ );
+}
+
+class Andes45GetLatecyDiv<int sew> {
+ int c = !cond(
+ !eq(sew, 8) : 12,
+ !eq(sew, 16) : 20,
+ !eq(sew, 32) : 36,
+ !eq(sew, 64) : 68
+ );
+}
+
+// (VLEN/DLEN)*LMUL*SEW+(VLEN/DLEN)*LMUL*2+1
+// = (VLEN/DLEN)*LMUL*(SEW+2)+1
+class Andes45GetCyclesDiv<string mx, int sew> {
+ int a = !mul(Andes45VLEN_DLEN_RATIO, !add(sew, 2));
+ int b = !cond(
+ !eq(mx, "M1") : !mul(a, 1),
+ !eq(mx, "M2") : !mul(a, 2),
+ !eq(mx, "M4") : !mul(a, 4),
+ !eq(mx, "M8") : !mul(a, 8),
+ !eq(mx, "MF2") : !mul(a, 1),
+ !eq(mx, "MF4") : !mul(a, 1),
+ !eq(mx, "MF8") : !mul(a, 1)
+ );
+
+ int c = !add(b, 1);
+}
+
+class Andes45GetFDivFactor<int sew> {
+ int c = !cond(
+ !eq(sew, 16) : 22,
+ !eq(sew, 32) : 36,
+ !eq(sew, 64) : 64
+ );
+}
+
+class Andes45GetFSqrtFactor<int sew> {
+ int c = !cond(
+ !eq(sew, 16) : 20,
+ !eq(sew, 32) : 34,
+ !eq(sew, 64) : 62
+ );
+}
+
+// (VLEN/DLEN)*LMUL+LOG2(DLEN/64)*2+LOG2(64/SEW)
+class Andes45GetReductionCycles<string mx, int sew> {
+ int d = Andes45GetCyclesDefault<mx>.c;
+ int c = !add(d,
+ !add(!mul(!logtwo(!div(Andes45DLEN, 64)), 2),
+ !logtwo(!div(64, sew))));
+}
+
+// (VLEN/DLEN)*LMUL*2+LOG2(DLEN/64)*2+LOG2(64/2/SEW)
+class Andes45GetReductionCyclesWidening<string mx, int sew> {
+ int w = !mul(Andes45GetCyclesDefault<mx>.c, 2);
+ int c = !add(w,
+ !add(!mul(!logtwo(!div(Andes45DLEN, 64)), 2),
+ !logtwo(!div(64, sew))));
+}
+
+// (VLEN/DLEN)*LMUL+LOG2(DLEN/SEW)
+class Andes45GetFReductionCycles<string mx, int sew> {
+ int d = Andes45GetCyclesDefault<mx>.c;
+ int c = !add(d, !logtwo(!div(Andes45DLEN, sew)));
+}
+
+// (VLEN/DLEN)*LMUL*2+LOG2(DLEN/SEW)-1
+class Andes45GetFWReductionCycles<string mx, int sew> {
+ int a = !mul(Andes45GetCyclesDefault<mx>.c, 2);
+ int b = !add(a, !logtwo(!div(Andes45DLEN, sew)));
+ int c = !sub(b, 1);
+}
+
+// (VLEN*LMUL)/SEW
+class Andes45GetOrderedFReductionCycles<string mx, int sew> {
+ int b = !cond(
+ !eq(mx, "M1") : !mul(Andes45VLEN, 1),
+ !eq(mx, "M2") : !mul(Andes45VLEN, 2),
+ !eq(mx, "M4") : !mul(Andes45VLEN, 4),
+ !eq(mx, "M8") : !mul(Andes45VLEN, 8),
+ !eq(mx, "MF2") : !mul(Andes45VLEN, 1),
+ !eq(mx, "MF4") : !mul(Andes45VLEN, 1),
+ !eq(mx, "MF8") : !mul(Andes45VLEN, 1)
+ );
+
+ int c = !div(b, sew);
+}
+
+// (VLEN*LMUL)/SEW
+class Andes45GetOrderedFWReductionCycles<string mx, int sew> {
+ int b = !cond(
+ !eq(mx, "M1") : !mul(Andes45VLEN, 1),
+ !eq(mx, "M2") : !mul(Andes45VLEN, 2),
+ !eq(mx, "M4") : !mul(Andes45VLEN, 4),
+ !eq(mx, "M8") : !mul(Andes45VLEN, 8),
+ !eq(mx, "MF2") : !mul(Andes45VLEN, 1),
+ !eq(mx, "MF4") : !mul(Andes45VLEN, 1),
+ !eq(mx, "MF8") : !mul(Andes45VLEN, 1)
+ );
+
+ int c = !div(b, sew);
+}
+
+
def Andes45Model : SchedMachineModel {
let MicroOpBufferSize = 0; // Andes45 is in-order processor
let IssueWidth = 2; // 2 micro-ops dispatched per cycle
@@ -32,6 +263,15 @@ let SchedModel = Andes45Model in {
// - Floating Point Divide / SQRT Unit (FDIV)
// - Floating Point Move Unit (FMV)
// - Floating Point Misc Unit (FMISC)
+//
+// Andes 45 series VPU
+// - Vector Arithmetic and Logical Unit (VALU)
+// - Vector Multiply Accumulate Unit (VMAC)
+// - Vector Divide Unit (VDIV)
+// - Vector Permutation Unit (VPERMUT)
+// - Vector Mask Unit (VMASK)
+// - Vector Floating-Point Miscellaneous Unit (VFMIS)
+// - Vector Floating-Point Divide Unit (VFDIV)
//===----------------------------------------------------------------------===//
let BufferSize = 0 in {
@@ -44,6 +284,24 @@ def Andes45FMAC : ProcResource<1>;
def Andes45FDIV : ProcResource<1>;
def Andes45FMV : ProcResource<1>;
def Andes45FMISC : ProcResource<1>;
+
+def Andes45VALU : ProcResource<1>;
+def Andes45VMAC : ProcResource<1>;
+def Andes45VFMIS : ProcResource<1>;
+def Andes45VPERMUT : ProcResource<1>;
+def Andes45VDIV : ProcResource<1>;
+def Andes45VFDIV : ProcResource<1>;
+def Andes45VMASK : ProcResource<1>;
+def Andes45VLSU : ProcResource<1>;
+
+def Andes45VPU : ProcResGroup<[Andes45VALU,
+ Andes45VMAC,
+ Andes45VFMIS,
+ Andes45VPERMUT,
+ Andes45VDIV,
+ Andes45VFDIV,
+ Andes45VMASK,
+ Andes45VLSU]>;
}
// Integer arithmetic and logic
@@ -333,10 +591,843 @@ def : ReadAdvance<ReadSingleBit, 0>;
def : ReadAdvance<ReadSingleBitImm, 0>;
def : ReadAdvance<ReadCSR, 0>;
+// RVV Scheduling
+
+// 6. Configuration-Setting Instructions
+def : WriteRes<WriteVSETVLI, [Andes45CSR]>;
+def : WriteRes<WriteVSETIVLI, [Andes45CSR]>;
+def : WriteRes<WriteVSETVL, [Andes45CSR]>;
+
+// 7. Vector Loads and Stores
+
+// Unit-stride loads and stores.
+
+// The latency for loads is (4+VLSU_MEM_LATENCY)
+// The throughput for loads and stores is (VLEN/VLSU_MEM_DW)*EMUL.
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesLoadStore<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(4, VLSU_MEM_LATENCY), ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVLDE", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDFF", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDM", [Andes45VLSU], mx, IsWorstCase>;
+ }
+ let Latency = 1, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVSTE", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTM", [Andes45VLSU], mx, IsWorstCase>;
+ }
+}
+
+// Strided loads and stores.
+
+// Strided loads and stores operate at one element per cycles.
+// We uses the SEW to compute the number of elements for throughput.
+// The latency for loads is (4+VLSU_MEM_LATENCY+(DLEN/EEW)).
+// The throughput for loads and stores is (VLEN/SEW)
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, 8>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(4, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, 8))),
+ ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVLDS8", [Andes45VLSU], mx, IsWorstCase>;
+ let Latency = 1, ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVSTS8", [Andes45VLSU], mx, IsWorstCase>;
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, 16>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(4, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, 16))),
+ ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVLDS16", [Andes45VLSU], mx, IsWorstCase>;
+ let Latency = 1, ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVSTS16", [Andes45VLSU], mx, IsWorstCase>;
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, 32>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(4, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, 32))),
+ ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVLDS32", [Andes45VLSU], mx, IsWorstCase>;
+ let Latency = 1, ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVSTS32", [Andes45VLSU], mx, IsWorstCase>;
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, 64>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(4, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, 64))),
+ ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVLDS64", [Andes45VLSU], mx, IsWorstCase>;
+ let Latency = 1, ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVSTS64", [Andes45VLSU], mx, IsWorstCase>;
+}
+
+// Indexed loads and stores
+
+// Indexed loads and stores operate at one element per cycles.
+// We uses the SEW to compute the number of elements for throughput.
+// The latency for loads is (5+VLSU_MEM_LATENCY+(DLEN/EEW)).
+// The throughput for loads and stores is (VL+EMUL-1).
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, 8>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(5, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, 8))),
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVLDUX8", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX8", [Andes45VLSU], mx, IsWorstCase>;
+ }
+ let Latency = 1,
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVSTUX8", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX8", [Andes45VLSU], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, 16>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(5, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, 16))),
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVLDUX16", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX16", [Andes45VLSU], mx, IsWorstCase>;
+ }
+ let Latency = 1,
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVSTUX16", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX16", [Andes45VLSU], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, 32>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(5, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, 32))),
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVLDUX32", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX32", [Andes45VLSU], mx, IsWorstCase>;
+ }
+ let Latency = 1,
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVSTUX32", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX32", [Andes45VLSU], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, 64>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(5, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, 64))),
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVLDUX64", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX64", [Andes45VLSU], mx, IsWorstCase>;
+ }
+ let Latency = 1,
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVSTUX64", [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX64", [Andes45VLSU], mx, IsWorstCase>;
+ }
+}
+
+// TODO: Please confirm again the throughput and latency for load/store
+// whole register
+// VLD*R is LMUL aware
+let Latency = 6, ReleaseAtCycles = [2] in
+ def : WriteRes<WriteVLD1R, [Andes45VLSU]>;
+let Latency = 6, ReleaseAtCycles = [4] in
+ def : WriteRes<WriteVLD2R, [Andes45VLSU]>;
+let Latency = 6, ReleaseAtCycles = [8] in
+ def : WriteRes<WriteVLD4R, [Andes45VLSU]>;
+let Latency = 6, ReleaseAtCycles = [16] in
+ def : WriteRes<WriteVLD8R, [Andes45VLSU]>;
+// VST*R is LMUL aware
+let Latency = 1, ReleaseAtCycles = [2] in
+ def : WriteRes<WriteVST1R, [Andes45VLSU]>;
+let Latency = 1, ReleaseAtCycles = [4] in
+ def : WriteRes<WriteVST2R, [Andes45VLSU]>;
+let Latency = 1, ReleaseAtCycles = [8] in
+ def : WriteRes<WriteVST4R, [Andes45VLSU]>;
+let Latency = 1, ReleaseAtCycles = [16] in
+ def : WriteRes<WriteVST8R, [Andes45VLSU]>;
+
+// Unit-Stride Segmented Loads and Stores
+
+// The latency for loads is (4+VLSU_MEM_LATENCY+EMUL* NFIELDS+2)
+// The throughput for loads and stores is (VLEN/VLSU_MEM_DW)*EMUL*NFIELDS.
+foreach mx = SchedMxList in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar Cycles = Andes45GetCyclesLoadStore<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ foreach nf=2-8 in {
+ defvar Size = !mul(Andes45GetLMULValue<mx>.c, nf);
+ let Latency = !add(4, !add(VLSU_MEM_LATENCY, !add(Size, 2))),
+ ReleaseAtCycles = [!mul(Cycles, nf)] in {
+ defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ }
+ // TODO
+ let Latency = 1, ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ }
+ }
+}
+
+// Strided Segmented Loads and Stores
+
+// The latency for loads is (5+VLSU_MEM_LATENCY+(DLEN/EEW))
+// The throughput for loads and stores is VL.
+foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, eew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(5, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, eew))),
+ ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ let Latency = 1, ReleaseAtCycles = [Cycles] in
+ defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ }
+ }
+}
+
+// Indexed Segmented Loads and Stores
+
+// The latency for loads is (6+VLSU_MEM_LATENCY+(DLEN/EEW))
+// The throughput for loads and stores is (VL+EMUL-1).
+foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar Cycles = Andes45GetCyclesOnePerElement<mx, eew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(6, !add(VLSU_MEM_LATENCY, !div(Andes45DLEN, eew))),
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ }
+ let Latency = 1,
+ ReleaseAtCycles = [!add(Cycles, !sub(Andes45GetLMULValue<mx>.c, 1))] in {
+ defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew,
+ [Andes45VLSU], mx, IsWorstCase>;
+ }
+ }
+ }
+}
+
+// 11. Vector Integer Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVIALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovI", [Andes45VALU], mx, IsWorstCase>;
+ }
+ // Mask results can't chain.
+ let Latency = !add(Cycles, 2),
+ ReleaseAtCycles = [!add(Cycles, !ne(Andes45VLEN, Andes45DLEN))] in {
+ defm "" : LMULWriteResMX<"WriteVICmpV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [Andes45VALU], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVIMulV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulX", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddX", [Andes45VMAC], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Latency = Andes45GetLatecyDiv<sew>.c;
+ defvar Cycles = Andes45GetCyclesDiv<mx, sew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Latency, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [Andes45VDIV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [Andes45VDIV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVExtV", [Andes45VPERMUT], mx, IsWorstCase>;
+ }
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ defvar Cycles = Andes45GetCyclesWidening<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = 2, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVIWALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUI", [Andes45VALU], mx, IsWorstCase>;
+ }
+ let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVIWMulV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulX", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddX", [Andes45VMAC], mx, IsWorstCase>;
+ }
+}
+
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar Latency = Andes45GetLatencyNarrowing<mx>.c;
+ defvar Cycles = Andes45GetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Latency, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVNShiftV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftI", [Andes45VALU], mx, IsWorstCase>;
+ }
+}
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVSALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [Andes45VALU], mx, IsWorstCase>;
+ }
+ let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVSMulV", [Andes45VMAC], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulX", [Andes45VMAC], mx, IsWorstCase>;
+ }
+}
+
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar Latency = Andes45GetLatencyNarrowing<mx>.c;
+ defvar Cycles = Andes45GetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Latency, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVNClipV", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipX", [Andes45VALU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [Andes45VALU], mx, IsWorstCase>;
+ }
+}
+
+// 13. Vector Floating-Point Instructions
+foreach mx = SchedMxListF in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ // The latency for the CPU configured as 'FP32' is 5, and as 'FP32+FP64' is 6.
+ // In most cases, CPU would be configured as "FP32+FP64".
+ let Latency = 6, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ }
+ let Latency = 3, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+ let Latency = 2, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListF>.c;
+ let Latency = 3, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [Andes45VFMIS], mx, IsWorstCase>;
+ }
+ let Latency = 2, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFClassV", [Andes45VFMIS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMergeV", [Andes45VFMIS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMovV", [Andes45VFMIS], mx, IsWorstCase>;
+ }
+ // Mask results can't chain.
+ let Latency = !add(Cycles, 2),
+ ReleaseAtCycles = [!add(Cycles, !ne(Andes45VLEN, Andes45DLEN))] in {
+ defm "" : LMULWriteResMX<"WriteVFCmpV", [Andes45VFMIS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCmpF", [Andes45VFMIS], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListF in {
+ defvar Cycles = !mul(Andes45GetCyclesDefault<mx>.c, 6);
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = 7, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [Andes45VFDIV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar Factor = Andes45GetFDivFactor<sew>.c;
+ defvar Cycles = !mul(Andes45GetCyclesDefault<mx>.c, Factor);
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ let Latency = !add(2, Factor), ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [Andes45VFDIV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [Andes45VFDIV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar Factor = Andes45GetFSqrtFactor<sew>.c;
+ defvar Cycles = !mul(Andes45GetCyclesDefault<mx>.c, Factor);
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ let Latency = !add(2, Factor), ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [Andes45VFDIV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ defvar Cycles = Andes45GetCyclesWidening<mx>.c;
+ foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
+ let Latency = 3, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+ }
+}
+foreach mx = SchedMxListFW in {
+ defvar Cycles = Andes45GetCyclesWidening<mx>.c;
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ // The latency for the CPU configured as 'FP32' is 5, and as 'FP32+FP64' is 6.
+ // In most cases, CPU would be configured as "FP32+FP64".
+ let Latency = 6, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [Andes45VMAC], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [Andes45VMAC], mx, sew, IsWorstCase>;
+ }
+ let Latency = 3, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+ }
+
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListFW>.c;
+ let Latency = 3, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [Andes45VFMIS], mx, IsWorstCase>;
+ }
+}
+
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar Latency = !add(Andes45GetLatencyNarrowing<mx>.c, 1);
+ defvar Cycles = Andes45GetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Latency, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [Andes45VFMIS], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxListFW in {
+ defvar Cycles = Andes45GetCyclesNarrowing<mx>.c;
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar Latency = !add(Andes45GetLatencyNarrowing<mx>.c, 1);
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = Latency, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [Andes45VFMIS], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// 14. Vector Reduction Operations
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = Andes45GetReductionCycles<mx, sew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = !add(Cycles, 1),
+ ReleaseAtCycles = [!add(Cycles, !ne(Andes45VLEN, Andes45DLEN))] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [Andes45VALU],
+ mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [Andes45VALU],
+ mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListWRed in {
+ foreach sew = SchedSEWSet<mx, 0, 1>.val in {
+ defvar Cycles = Andes45GetReductionCyclesWidening<mx, sew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
+ let Latency = !add(Cycles, 1),
+ ReleaseAtCycles = [!add(Cycles, !ne(Andes45VLEN, Andes45DLEN))] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [Andes45VALU],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar Cycles = Andes45GetFReductionCycles<mx, sew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ // 4*vfredusum-micro-ops+2
+ let Latency = !add(!mul(4, Cycles), 2),
+ // 1+4*(vfredusum-micro-ops-1)+(VLEN!=DLEN)
+ ReleaseAtCycles = [!add(1, !add(!mul(4, !sub(Cycles, 1)), !ne(Andes45VLEN, Andes45DLEN)))] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [Andes45VMAC],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar Cycles = Andes45GetOrderedFReductionCycles<mx, sew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ // 4*vfredosum-micro-ops+2
+ let Latency = !add(!mul(4, Cycles), 2),
+ // 1+4*(vfredosum-micro-ops-1)+(VLEN!=DLEN)
+ ReleaseAtCycles = [!add(1, !add(!mul(4, !sub(Cycles, 1)), !ne(Andes45VLEN, Andes45DLEN)))] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [Andes45VMAC],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar Cycles = Andes45GetReductionCycles<mx, sew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ let Latency = !add(Cycles, 1),
+ ReleaseAtCycles = [!add(Cycles, !ne(Andes45VLEN, Andes45DLEN))] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [Andes45VFMIS],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListFWRed in {
+ foreach sew = SchedSEWSet<mx, 1, 1>.val in {
+ defvar Cycles = Andes45GetFWReductionCycles<mx, sew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ // 4*vfwredusum-micro-ops+2
+ let Latency = !add(!mul(4, Cycles), 2),
+ // 1+4*(vfwredusum-micro-ops-1)+(VLEN!=DLEN)
+ ReleaseAtCycles = [!add(1, !add(!mul(4, !sub(Cycles, 1)), !ne(Andes45VLEN, Andes45DLEN)))] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [Andes45VMAC],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListFWRed in {
+ foreach sew = SchedSEWSet<mx, 1, 1>.val in {
+ defvar Cycles = Andes45GetOrderedFWReductionCycles<mx, sew>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ // 4*vfwredosum-micro-ops+2
+ let Latency = !add(!mul(4, Cycles), 2),
+ // 1+4*(vfwredosum-micro-ops-1)+(VLEN != DLEN)
+ ReleaseAtCycles = [!add(1, !add(!mul(4, !sub(Cycles, 1)), !ne(Andes45VLEN, Andes45DLEN)))] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [Andes45VMAC],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+// 15. Vector Mask Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 3, ReleaseAtCycles = [Andes45VLEN_DLEN_RATIO] in {
+ defm "" : LMULWriteResMX<"WriteVMALUV", [Andes45VMASK], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [Andes45VMASK], mx, IsWorstCase>;
+ }
+ let Latency = !add(3, !ne(Andes45VLEN, Andes45DLEN)),
+ ReleaseAtCycles = [Andes45VLEN_DLEN_RATIO] in {
+ defm "" : LMULWriteResMX<"WriteVMPopV", [Andes45VMASK], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMFFSV", [Andes45VMASK], mx, IsWorstCase>;
+ }
+}
+// TODO: viota and vid have different latency and throughput if VLEN/DLEN=2.
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVIotaV", [Andes45VMASK], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIdxV", [Andes45VMASK], mx, IsWorstCase>;
+ }
+}
+
+// 16. Vector Permutation Instructions
+let Latency = 2, ReleaseAtCycles = [Andes45VLEN_DLEN_RATIO] in {
+ def : WriteRes<WriteVMovSX, [Andes45VPERMUT]>;
+ def : WriteRes<WriteVMovSF, [Andes45VPERMUT]>;
+}
+let Latency = 3, ReleaseAtCycles = [Andes45VLEN_DLEN_RATIO] in {
+ def : WriteRes<WriteVMovXS, [Andes45VPERMUT]>;
+ def : WriteRes<WriteVMovFS, [Andes45VPERMUT]>;
+}
+
+// TODO:
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRGatherVI", [Andes45VPERMUT], mx, IsWorstCase>;
+ }
+}
+
+// TODO:
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [Andes45VPERMUT], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [Andes45VPERMUT], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [Andes45VPERMUT], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// TODO:
+foreach mx = SchedMxList in {
+ defvar Cycles = Andes45GetCyclesDefault<mx>.c;
+ defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideI", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1X", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1F", [Andes45VPERMUT], mx, IsWorstCase>;
+ }
+}
+
+// VMov*V is LMUL Aware
+let Latency = 2, ReleaseAtCycles = [!mul(Andes45VLEN_DLEN_RATIO, 1)] in
+ def : WriteRes<WriteVMov1V, [Andes45VPERMUT]>;
+let Latency = 2, ReleaseAtCycles = [!mul(Andes45VLEN_DLEN_RATIO, 2)] in
+ def : WriteRes<WriteVMov2V, [Andes45VPERMUT]>;
+let Latency = 2, ReleaseAtCycles = [!mul(Andes45VLEN_DLEN_RATIO, 4)] in
+ def : WriteRes<WriteVMov4V, [Andes45VPERMUT]>;
+let Latency = 2, ReleaseAtCycles = [!mul(Andes45VLEN_DLEN_RATIO, 8)] in
+ def : WriteRes<WriteVMov8V, [Andes45VPERMUT]>;
+
+// Others
+def : WriteRes<WriteRdVLENB, [Andes45CSR]>;
+
+// 6. Configuration-Setting Instructions
+def : ReadAdvance<ReadVSETVLI, 0>;
+def : ReadAdvance<ReadVSETVL, 0>;
+
+// 7. Vector Loads and Stores
+def : ReadAdvance<ReadVLDX, 0>;
+def : ReadAdvance<ReadVSTX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+def : ReadAdvance<ReadVLDSX, 0>;
+def : ReadAdvance<ReadVSTSX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVST1R, 0>;
+def : ReadAdvance<ReadVST2R, 0>;
+def : ReadAdvance<ReadVST4R, 0>;
+def : ReadAdvance<ReadVST8R, 0>;
+
+// 11. Vector Integer Arithmetic Instructions
+defm : LMULReadAdvance<"ReadVIALUV", 0>;
+defm : LMULReadAdvance<"ReadVIALUX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
+defm : LMULReadAdvance<"ReadVExtV", 0>;
+defm : LMULReadAdvance<"ReadVICALUV", 0>;
+defm : LMULReadAdvance<"ReadVICALUX", 0>;
+defm : LMULReadAdvance<"ReadVShiftV", 0>;
+defm : LMULReadAdvance<"ReadVShiftX", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
+defm : LMULReadAdvance<"ReadVICmpV", 0>;
+defm : LMULReadAdvance<"ReadVICmpX", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;
+defm : LMULReadAdvance<"ReadVIMulV", 0>;
+defm : LMULReadAdvance<"ReadVIMulX", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
+defm : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm : LMULReadAdvance<"ReadVIMovV", 0>;
+defm : LMULReadAdvance<"ReadVIMovX", 0>;
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
+
+// 13. Vector Floating-Point Instructions
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
+defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
+defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
+
+// 14. Vector Reduction Operations
+def : ReadAdvance<ReadVIRedV, 0>;
+def : ReadAdvance<ReadVIRedV0, 0>;
+def : ReadAdvance<ReadVIWRedV, 0>;
+def : ReadAdvance<ReadVIWRedV0, 0>;
+def : ReadAdvance<ReadVFRedV, 0>;
+def : ReadAdvance<ReadVFRedV0, 0>;
+def : ReadAdvance<ReadVFRedOV, 0>;
+def : ReadAdvance<ReadVFRedOV0, 0>;
+def : ReadAdvance<ReadVFWRedV, 0>;
+def : ReadAdvance<ReadVFWRedV0, 0>;
+def : ReadAdvance<ReadVFWRedOV, 0>;
+def : ReadAdvance<ReadVFWRedOV0, 0>;
+
+// 15. Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
+defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
+
+// 16. Vector Permutation Instructions
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
+defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVMov1V, 0>;
+def : ReadAdvance<ReadVMov2V, 0>;
+def : ReadAdvance<ReadVMov4V, 0>;
+def : ReadAdvance<ReadVMov8V, 0>;
+
+// Others
+def : ReadAdvance<ReadVMask, 0>;
+def : ReadAdvance<ReadVPassthru_WorstCase, 0>;
+foreach mx = SchedMxList in {
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;
+ foreach sew = SchedSEWSet<mx>.val in
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;
+}
+
//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedQ;
-defm : UnsupportedSchedV;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s
index d1ab4b3b6a7e0..1a7812e70438d 100644
--- a/llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s
@@ -67,26 +67,34 @@ fcvt.s.w ft0, a0
# CHECK-NEXT: [5] - Andes45FMV
# CHECK-NEXT: [6] - Andes45LSU
# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - - 56.00 4.00 4.00 2.00 - -
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - - 56.00 4.00 4.00 2.00 - - - - - - - - - -
# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - fadd.s ft0, fa0, fa1
-# CHECK-NEXT: - - - 19.00 - - - - - fdiv.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - 1.00 - - - - fadd.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - 1.00 - - - - fmul.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - 1.00 - - - - fmadd.s ft0, fa0, fa1, fa2
-# CHECK-NEXT: - - - 19.00 - - - - - fdiv.s ft0, fa0, fa1
-# CHECK-NEXT: - - - 18.00 - - - - - fsqrt.s ft0, fa0
-# CHECK-NEXT: - - - - - - 1.00 - - fsgnj.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - - - 1.00 - - fmv.x.w a0, fa0
-# CHECK-NEXT: - - - - - 1.00 - - - fmin.s ft0, fa0, fa1
-# CHECK-NEXT: - - - - - 1.00 - - - fclass.s a0, fa0
-# CHECK-NEXT: - - - - - 1.00 - - - feq.s a0, fa0, fa1
-# CHECK-NEXT: - - - - - 1.00 - - - fcvt.s.w ft0, a0
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - fadd.s ft0, fa0, fa1
+# CHECK-NEXT: - - - 19.00 - - - - - - - - - - - - - fdiv.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - fadd.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - fmul.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - fmadd.s ft0, fa0, fa1, fa2
+# CHECK-NEXT: - - - 19.00 - - - - - - - - - - - - - fdiv.s ft0, fa0, fa1
+# CHECK-NEXT: - - - 18.00 - - - - - - - - - - - - - fsqrt.s ft0, fa0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - fsgnj.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - fmv.x.w a0, fa0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - fmin.s ft0, fa0, fa1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - fclass.s a0, fa0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - feq.s a0, fa0, fa1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - fcvt.s.w ft0, a0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
index d90dce8c5c3fc..3227ecfa4a372 100644
--- a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
@@ -133,55 +133,63 @@ bext a0, a0, a0
# CHECK-NEXT: [5] - Andes45FMV
# CHECK-NEXT: [6] - Andes45LSU
# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: 10.00 11.00 1.00 - - - - 16.00 80.00
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: 10.00 11.00 1.00 - - - - 16.00 80.00 - - - - - - - -
# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - 1.00 - - - - - - - add a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - sub a1, a1, a1
-# CHECK-NEXT: - 1.00 - - - - - - - addw a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - subw a0, a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - slli a0, a0, 4
-# CHECK-NEXT: 1.00 - - - - - - - - slliw a0, a0, 4
-# CHECK-NEXT: - 1.00 - - - - - - - srl a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - srlw a0, a0, a0
-# CHECK-NEXT: - - - - - - - - 1.00 mul a0, a0, a0
-# CHECK-NEXT: - - - - - - - - 1.00 mulw a0, a0, a0
-# CHECK-NEXT: - - - - - - - - 39.00 div a0, a0, a0
-# CHECK-NEXT: - - - - - - - - 39.00 divw a0, a0, a0
-# CHECK-NEXT: - - - - - - - 1.00 - lb a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - lh a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - lw a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - ld a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - flw fa0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - fld fa0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - sb a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - sh a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - sw a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - sd a0, 4(a1)
-# CHECK-NEXT: - - - - - - - 1.00 - amoswap.w a0, a1, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - amoswap.d a0, a1, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - lr.w a0, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - lr.d a0, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - sc.w a0, a1, (a0)
-# CHECK-NEXT: - - - - - - - 1.00 - sc.d a0, a1, (a0)
-# CHECK-NEXT: - - 1.00 - - - - - - csrrw a0, mstatus, zero
-# CHECK-NEXT: - 1.00 - - - - - - - sh1add a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - sh1add.uw a0, a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - rori a0, a0, 4
-# CHECK-NEXT: 1.00 - - - - - - - - roriw a0, a0, 4
-# CHECK-NEXT: - 1.00 - - - - - - - rol a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - rolw a0, a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - clz a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - clzw a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - clmul a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - bclri a0, a0, 4
-# CHECK-NEXT: - 1.00 - - - - - - - bclr a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - bexti a0, a0, 4
-# CHECK-NEXT: - 1.00 - - - - - - - bext a0, a0, a0
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - sub a1, a1, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - subw a0, a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - slli a0, a0, 4
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - slliw a0, a0, 4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - srl a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - srlw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - mul a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - mulw a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 39.00 - - - - - - - - div a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 39.00 - - - - - - - - divw a0, a0, a0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lb a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lh a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lw a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ld a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - flw fa0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - fld fa0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sb a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sh a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sw a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sd a0, 4(a1)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - amoswap.w a0, a1, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - amoswap.d a0, a1, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lr.w a0, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lr.d a0, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sc.w a0, a1, (a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sc.d a0, a1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - csrrw a0, mstatus, zero
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - sh1add a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - sh1add.uw a0, a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - rori a0, a0, 4
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - roriw a0, a0, 4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - rol a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - rolw a0, a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - clz a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - clzw a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - clmul a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - bclri a0, a0, 4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - bclr a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - bexti a0, a0, 4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - bext a0, a0, a0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 012
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
new file mode 100644
index 0000000000000..570456c7a1a7a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s
@@ -0,0 +1,6838 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Basic arithmetic operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vsub.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vsub.vx v8, v8, x30
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+vsub.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+
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+vadc.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vadc.vim v8, v8, 12, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vsetvli x28, x0, e64, m8, tu, mu
+vsbc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+
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+
+vsetvli x28, x0, e8, mf2, tu, mu
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+
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+
+vsetvli x28, x0, e8, mf2, tu, mu
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+
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+
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+vwsubu.vx v8, v16, x30
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+vwsubu.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
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+vsetvli x28, x0, e16, mf4, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssubu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssubu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vssub.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vssub.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssub.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwaddu.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwaddu.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwadd.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwadd.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwsubu.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwsubu.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwsub.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwsub.wx v8, v16, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VWSUB_WX vwsub.wx v8, v16, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 1120.00 - - - - - - 3408.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wx v8, v16, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s
new file mode 100644
index 0000000000000..eee23b71e1ff5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s
@@ -0,0 +1,4346 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Bitwise and logical operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vnsrl.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vnsrl.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vnsrl.wi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vnclipu.wi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vnclipu.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vnclipu.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vnclipu.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vnclipu.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vnclip.wi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vnclip.wi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vnclip.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vnclip.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vnclip.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vnclip.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsll.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vsll.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vsll.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vsll.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vsll.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vsll.vi v8, v8, 12
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+vssra.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vssra.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssra.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vssrl.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vssrl.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssrl.vx v8, v8, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2],Andes45VPU[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4],Andes45VPU[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8],Andes45VPU[8] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VSSRL_VX vssrl.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 708.00 - - - - - - 2160.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
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+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s
new file mode 100644
index 0000000000000..527800cc5da90
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s
@@ -0,0 +1,2722 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Comparison operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmseq.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmseq.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmseq.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vmseq.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vmseq.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsle.vv v8, v8, v8
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+vmsgtu.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vmsgtu.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vmsgtu.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vmsgtu.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vmsgtu.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vmsgtu.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vmsgtu.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmsgtu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmsgtu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vmsgt.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vmsgt.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmsgt.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmsgt.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmsltu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmsltu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmsltu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmsltu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmslt.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmslt.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmslt.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmslt.vx v8, v8, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VALU,Andes45VPU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2],Andes45VPU[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4],Andes45VPU[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8],Andes45VPU[8] VMSLT_VX vmslt.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 440.00 - - - - - - 1320.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vx v8, v8, t5
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s
new file mode 100644
index 0000000000000..b2fc3ad01e88b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s
@@ -0,0 +1,1775 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Conversion operations
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf2 v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf2 v8, v16
+
+vsetvli x28, x0, e32, mf2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf4 v8, v16
+
+vsetvli x28, x0, e32, mf2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf4 v8, v16
+
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf8 v8, v16
+
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf8 v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.f.x.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.x.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.xu.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.x.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.x.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.xu.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.x.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.xu.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.x.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.xu.f.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VFMIS[4],Andes45VPU[4] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VFMIS[8],Andes45VPU[8] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 Andes45VFMIS[2],Andes45VPU[2] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 Andes45VFMIS[4],Andes45VPU[4] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 Andes45VFMIS[8],Andes45VPU[8] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 281.00 - - - - - - - - - 753.00 - - - 188.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf2 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf4 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf8 v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfcvt.f.xu.v v8, v8
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfwcvt.xu.f.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s
new file mode 100644
index 0000000000000..abaf93262bd5e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s
@@ -0,0 +1,2203 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Fused multiply-add operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmacc.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmacc.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmadd.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmadd.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsac.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsac.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsub.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsub.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmacc.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmacc.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmsac.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmsac.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmacc.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmsac.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmsac.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 353.00 - - - - - - - - - - - 1112.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
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+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwnmsac.vv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s
new file mode 100644
index 0000000000000..9904422aaf0a7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s
@@ -0,0 +1,5617 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Floating point operations
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfeq.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfge.vf v8, v8, ft0
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+vfmadd.vf v8, f8, v8
+
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+vfnmacc.vv v8, v8, v8
+
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+
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+vfnmsub.vv v8, v8, v8
+
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+vfrdiv.vf v8, v8, ft0
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+vfrdiv.vf v8, v8, ft0
+
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+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.wf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.wv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VFMIS,Andes45VPU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VFMIS[2],Andes45VPU[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VFMIS[4],Andes45VPU[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 Andes45VFMIS[8],Andes45VPU[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 24 44.00 24 Andes45VFDIV[44],Andes45VPU[44] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 88.00 24 Andes45VFDIV[88],Andes45VPU[88] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 24 176.00 24 Andes45VFDIV[176],Andes45VPU[176] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 38 36.00 38 Andes45VFDIV[36],Andes45VPU[36] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 38 36.00 38 Andes45VFDIV[36],Andes45VPU[36] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 38 72.00 38 Andes45VFDIV[72],Andes45VPU[72] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 38 144.00 38 Andes45VFDIV[144],Andes45VPU[144] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 38 288.00 38 Andes45VFDIV[288],Andes45VPU[288] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 66 64.00 66 Andes45VFDIV[64],Andes45VPU[64] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 66 128.00 66 Andes45VFDIV[128],Andes45VPU[128] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 66 256.00 66 Andes45VFDIV[256],Andes45VPU[256] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 66 512.00 66 Andes45VFDIV[512],Andes45VPU[512] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 24 44.00 24 Andes45VFDIV[44],Andes45VPU[44] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 88.00 24 Andes45VFDIV[88],Andes45VPU[88] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 24 176.00 24 Andes45VFDIV[176],Andes45VPU[176] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 38 36.00 38 Andes45VFDIV[36],Andes45VPU[36] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 38 36.00 38 Andes45VFDIV[36],Andes45VPU[36] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 38 72.00 38 Andes45VFDIV[72],Andes45VPU[72] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 38 144.00 38 Andes45VFDIV[144],Andes45VPU[144] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 38 288.00 38 Andes45VFDIV[288],Andes45VPU[288] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 66 64.00 66 Andes45VFDIV[64],Andes45VPU[64] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 66 128.00 66 Andes45VFDIV[128],Andes45VPU[128] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 66 256.00 66 Andes45VFDIV[256],Andes45VPU[256] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 66 512.00 66 Andes45VFDIV[512],Andes45VPU[512] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 22.00 24 Andes45VFDIV[22],Andes45VPU[22] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 24 44.00 24 Andes45VFDIV[44],Andes45VPU[44] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 88.00 24 Andes45VFDIV[88],Andes45VPU[88] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 24 176.00 24 Andes45VFDIV[176],Andes45VPU[176] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 38 36.00 38 Andes45VFDIV[36],Andes45VPU[36] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 38 36.00 38 Andes45VFDIV[36],Andes45VPU[36] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 38 72.00 38 Andes45VFDIV[72],Andes45VPU[72] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 38 144.00 38 Andes45VFDIV[144],Andes45VPU[144] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 38 288.00 38 Andes45VFDIV[288],Andes45VPU[288] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 66 64.00 66 Andes45VFDIV[64],Andes45VPU[64] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 66 128.00 66 Andes45VFDIV[128],Andes45VPU[128] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 66 256.00 66 Andes45VFDIV[256],Andes45VPU[256] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 66 512.00 66 Andes45VFDIV[512],Andes45VPU[512] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 7 12.00 7 Andes45VFDIV[12],Andes45VPU[12] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 7 24.00 7 Andes45VFDIV[24],Andes45VPU[24] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 7 48.00 7 Andes45VFDIV[48],Andes45VPU[48] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 12.00 7 Andes45VFDIV[12],Andes45VPU[12] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 24.00 7 Andes45VFDIV[24],Andes45VPU[24] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 7 48.00 7 Andes45VFDIV[48],Andes45VPU[48] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 7 12.00 7 Andes45VFDIV[12],Andes45VPU[12] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 7 24.00 7 Andes45VFDIV[24],Andes45VPU[24] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 7 48.00 7 Andes45VFDIV[48],Andes45VPU[48] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 7 12.00 7 Andes45VFDIV[12],Andes45VPU[12] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 7 24.00 7 Andes45VFDIV[24],Andes45VPU[24] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 7 48.00 7 Andes45VFDIV[48],Andes45VPU[48] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 12.00 7 Andes45VFDIV[12],Andes45VPU[12] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 24.00 7 Andes45VFDIV[24],Andes45VPU[24] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 7 48.00 7 Andes45VFDIV[48],Andes45VPU[48] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 6.00 7 Andes45VFDIV[6],Andes45VPU[6] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 7 12.00 7 Andes45VFDIV[12],Andes45VPU[12] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 7 24.00 7 Andes45VFDIV[24],Andes45VPU[24] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 7 48.00 7 Andes45VFDIV[48],Andes45VPU[48] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 22 20.00 22 Andes45VFDIV[20],Andes45VPU[20] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 20.00 22 Andes45VFDIV[20],Andes45VPU[20] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 22 20.00 22 Andes45VFDIV[20],Andes45VPU[20] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 22 40.00 22 Andes45VFDIV[40],Andes45VPU[40] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 22 80.00 22 Andes45VFDIV[80],Andes45VPU[80] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 22 160.00 22 Andes45VFDIV[160],Andes45VPU[160] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 34.00 36 Andes45VFDIV[34],Andes45VPU[34] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 34.00 36 Andes45VFDIV[34],Andes45VPU[34] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 68.00 36 Andes45VFDIV[68],Andes45VPU[68] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 136.00 36 Andes45VFDIV[136],Andes45VPU[136] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 272.00 36 Andes45VFDIV[272],Andes45VPU[272] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 64 62.00 64 Andes45VFDIV[62],Andes45VPU[62] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 64 124.00 64 Andes45VFDIV[124],Andes45VPU[124] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 64 248.00 64 Andes45VFDIV[248],Andes45VPU[248] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 496.00 64 Andes45VFDIV[496],Andes45VPU[496] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC,Andes45VPU VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2],Andes45VPU[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4],Andes45VPU[4] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8],Andes45VPU[8] VFWSUB_WV vfwsub.wv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 915.00 - - - - - - - - 8120.00 1152.00 - 1414.00 - 30.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwsub.wv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mask.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mask.s
new file mode 100644
index 0000000000000..eabe716bcdb1a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mask.s
@@ -0,0 +1,1882 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Mask operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmand.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmnand.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmandn.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmxor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmnor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmorn.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmxnor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsbf.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsif.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsof.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m8, tu, mu
+vid.v v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vcpop.m x8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfirst.m x8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMASK[2],Andes45VPU[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMASK[4],Andes45VPU[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMASK[8],Andes45VPU[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMASK[2],Andes45VPU[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMASK[4],Andes45VPU[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMASK[8],Andes45VPU[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMASK[2],Andes45VPU[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMASK[4],Andes45VPU[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMASK[8],Andes45VPU[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMASK[2],Andes45VPU[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMASK[4],Andes45VPU[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMASK[8],Andes45VPU[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VMASK,Andes45VPU VFIRST_M vfirst.m s0, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 301.00 - - - - - - - - - - - - 345.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmmv.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmnot.m v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 - vid.v v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vcpop.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - vfirst.m s0, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s
new file mode 100644
index 0000000000000..3897a906d7bf7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s
@@ -0,0 +1,1126 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Min/max operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmax.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmax.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmaxu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmaxu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmin.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmin.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vminu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vminu.vx v8, v8, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMINU_VX vminu.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 176.00 - - - - - - 528.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s
new file mode 100644
index 0000000000000..4e5ccc1a8dbd5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s
@@ -0,0 +1,3002 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Multiplication and division operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmul.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmul.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vdiv.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vdiv.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vdivu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vdivu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vdivu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vdivu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vrem.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
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+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmulhsu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmul.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmul.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulu.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vsmul.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vsmul.vx v8, v8, x30
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21],Andes45VPU[21] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41],Andes45VPU[41] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81],Andes45VPU[81] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37],Andes45VPU[37] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73],Andes45VPU[73] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145],Andes45VPU[145] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69],Andes45VPU[69] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137],Andes45VPU[137] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273],Andes45VPU[273] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67],Andes45VPU[67] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133],Andes45VPU[133] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265],Andes45VPU[265] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529],Andes45VPU[529] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21],Andes45VPU[21] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41],Andes45VPU[41] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81],Andes45VPU[81] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37],Andes45VPU[37] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73],Andes45VPU[73] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145],Andes45VPU[145] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69],Andes45VPU[69] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137],Andes45VPU[137] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273],Andes45VPU[273] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67],Andes45VPU[67] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133],Andes45VPU[133] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265],Andes45VPU[265] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529],Andes45VPU[529] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21],Andes45VPU[21] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41],Andes45VPU[41] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81],Andes45VPU[81] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37],Andes45VPU[37] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73],Andes45VPU[73] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145],Andes45VPU[145] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69],Andes45VPU[69] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137],Andes45VPU[137] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273],Andes45VPU[273] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67],Andes45VPU[67] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133],Andes45VPU[133] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265],Andes45VPU[265] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529],Andes45VPU[529] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21],Andes45VPU[21] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41],Andes45VPU[41] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81],Andes45VPU[81] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37],Andes45VPU[37] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73],Andes45VPU[73] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145],Andes45VPU[145] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69],Andes45VPU[69] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137],Andes45VPU[137] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273],Andes45VPU[273] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67],Andes45VPU[67] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133],Andes45VPU[133] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265],Andes45VPU[265] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529],Andes45VPU[529] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21],Andes45VPU[21] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41],Andes45VPU[41] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81],Andes45VPU[81] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37],Andes45VPU[37] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73],Andes45VPU[73] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145],Andes45VPU[145] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69],Andes45VPU[69] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137],Andes45VPU[137] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273],Andes45VPU[273] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67],Andes45VPU[67] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133],Andes45VPU[133] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265],Andes45VPU[265] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529],Andes45VPU[529] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21],Andes45VPU[21] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41],Andes45VPU[41] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81],Andes45VPU[81] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37],Andes45VPU[37] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73],Andes45VPU[73] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145],Andes45VPU[145] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69],Andes45VPU[69] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137],Andes45VPU[137] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273],Andes45VPU[273] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67],Andes45VPU[67] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133],Andes45VPU[133] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265],Andes45VPU[265] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529],Andes45VPU[529] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21],Andes45VPU[21] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41],Andes45VPU[41] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81],Andes45VPU[81] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37],Andes45VPU[37] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73],Andes45VPU[73] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145],Andes45VPU[145] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69],Andes45VPU[69] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137],Andes45VPU[137] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273],Andes45VPU[273] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67],Andes45VPU[67] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133],Andes45VPU[133] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265],Andes45VPU[265] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529],Andes45VPU[529] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11],Andes45VPU[11] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21],Andes45VPU[21] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41],Andes45VPU[41] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81],Andes45VPU[81] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19],Andes45VPU[19] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37],Andes45VPU[37] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73],Andes45VPU[73] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145],Andes45VPU[145] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35],Andes45VPU[35] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69],Andes45VPU[69] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137],Andes45VPU[137] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273],Andes45VPU[273] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67],Andes45VPU[67] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133],Andes45VPU[133] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265],Andes45VPU[265] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529],Andes45VPU[529] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC,Andes45VPU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2],Andes45VPU[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4],Andes45VPU[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8],Andes45VPU[8] VSMUL_VX vsmul.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 486.00 - - - - - - - 16336.00 - - - 948.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vx v8, v8, t5
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+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s
new file mode 100644
index 0000000000000..50ab1b34529f6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s
@@ -0,0 +1,3522 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Permutation and shuffle operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.x v8, x8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.i v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.x.s x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.s.x v8, x8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv1r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv2r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv4r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv8r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+viota.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m8, tu, mu
+vcompress.vm v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vslide1up.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vslide1down.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vslideup.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vslideup.vi v8, v16, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vslideup.vi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vslidedown.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vslidedown.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vslidedown.vi v8, v16, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vslidedown.vi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e64, m1, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e64, m2, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e64, m4, tu, mu
+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e64, m8, tu, mu
+vrgather.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vrgather.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vrgather.vi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vrgatherei16.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e64, m1, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e64, m2, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e64, m4, tu, mu
+vrgatherei16.vv v8, v16, v24
+vsetvli x28, x0, e64, m8, tu, mu
+vrgatherei16.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vmerge.vim v8, v8, 12, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vmerge.vim v8, v8, 12, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vmerge.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vmerge.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 Andes45VPERMUT,Andes45VPU VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT,Andes45VPU VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4],Andes45VPU[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8],Andes45VPU[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMASK[2],Andes45VPU[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMASK[4],Andes45VPU[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMASK[8],Andes45VPU[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMASK[2],Andes45VPU[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMASK[4],Andes45VPU[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMASK[8],Andes45VPU[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMASK[2],Andes45VPU[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMASK[4],Andes45VPU[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMASK[8],Andes45VPU[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 Andes45VMASK,Andes45VPU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 Andes45VMASK[2],Andes45VPU[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VMASK[4],Andes45VPU[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 Andes45VMASK[8],Andes45VPU[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VALU,Andes45VPU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2],Andes45VPU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4],Andes45VPU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8],Andes45VPU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 Andes45VFMIS,Andes45VPU VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VFMIS[2],Andes45VPU[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 Andes45VFMIS[4],Andes45VPU[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 Andes45VFMIS[8],Andes45VPU[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT,Andes45VPU VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2],Andes45VPU[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 Andes45VPERMUT[4],Andes45VPU[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 Andes45VPERMUT[8],Andes45VPU[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 572.00 - - - - - - 396.00 - - 48.00 - - 66.00 1188.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vfslide1up.vf v8, v16, ft0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s
new file mode 100644
index 0000000000000..1364855c5c937
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s
@@ -0,0 +1,1842 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Reduction operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredand.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmax.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredminu.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmin.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredor.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredsum.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredxor.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vwredsum.vs v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredmax.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredmin.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredosum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredusum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfwredosum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfwredusum.vs v8, v8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VALU[7],Andes45VPU[7] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VALU[14],Andes45VPU[14] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VALU[7],Andes45VPU[7] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VALU[14],Andes45VPU[14] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VALU[7],Andes45VPU[7] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VALU[14],Andes45VPU[14] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VALU[7],Andes45VPU[7] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VALU[14],Andes45VPU[14] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VALU[7],Andes45VPU[7] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VALU[14],Andes45VPU[14] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VALU[7],Andes45VPU[7] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VALU[14],Andes45VPU[14] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VALU[7],Andes45VPU[7] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VALU[14],Andes45VPU[14] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VALU[7],Andes45VPU[7] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VALU[8],Andes45VPU[8] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VALU[14],Andes45VPU[14] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 26 25.00 26 Andes45VALU[25],Andes45VPU[25] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 25 24.00 25 Andes45VALU[24],Andes45VPU[24] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 24 23.00 24 Andes45VALU[23],Andes45VPU[23] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 14 13.00 14 Andes45VALU[13],Andes45VPU[13] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 18 17.00 18 Andes45VALU[17],Andes45VPU[17] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 26 25.00 26 Andes45VALU[25],Andes45VPU[25] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VALU[10],Andes45VPU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VALU[12],Andes45VPU[12] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VALU[16],Andes45VPU[16] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 25 24.00 25 Andes45VALU[24],Andes45VPU[24] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VALU[9],Andes45VPU[9] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VALU[11],Andes45VPU[11] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VALU[15],Andes45VPU[15] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 24 23.00 24 Andes45VALU[23],Andes45VPU[23] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VFMIS[9],Andes45VPU[9] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VFMIS[9],Andes45VPU[9] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VFMIS[9],Andes45VPU[9] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VFMIS[10],Andes45VPU[10] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VFMIS[12],Andes45VPU[12] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VFMIS[16],Andes45VPU[16] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VFMIS[8],Andes45VPU[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VFMIS[8],Andes45VPU[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VFMIS[9],Andes45VPU[9] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VFMIS[11],Andes45VPU[11] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VFMIS[15],Andes45VPU[15] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VFMIS[7],Andes45VPU[7] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VFMIS[8],Andes45VPU[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VFMIS[10],Andes45VPU[10] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VFMIS[14],Andes45VPU[14] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VFMIS[9],Andes45VPU[9] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VFMIS[9],Andes45VPU[9] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VFMIS[9],Andes45VPU[9] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VFMIS[10],Andes45VPU[10] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 Andes45VFMIS[12],Andes45VPU[12] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 16.00 17 Andes45VFMIS[16],Andes45VPU[16] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VFMIS[8],Andes45VPU[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VFMIS[8],Andes45VPU[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 9.00 10 Andes45VFMIS[9],Andes45VPU[9] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 11.00 12 Andes45VFMIS[11],Andes45VPU[11] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 15.00 16 Andes45VFMIS[15],Andes45VPU[15] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 7.00 8 Andes45VFMIS[7],Andes45VPU[7] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 Andes45VFMIS[8],Andes45VPU[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 Andes45VFMIS[10],Andes45VPU[10] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 Andes45VFMIS[14],Andes45VPU[14] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 258 253.00 258 Andes45VMAC[253],Andes45VPU[253] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 514 509.00 514 Andes45VMAC[509],Andes45VPU[509] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1026 1021.00 1026 Andes45VMAC[1021],Andes45VPU[1021] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 66 61.00 66 Andes45VMAC[61],Andes45VPU[61] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 66 61.00 66 Andes45VMAC[61],Andes45VPU[61] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 258 253.00 258 Andes45VMAC[253],Andes45VPU[253] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 514 509.00 514 Andes45VMAC[509],Andes45VPU[509] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 34 29.00 34 Andes45VMAC[29],Andes45VPU[29] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 66 61.00 66 Andes45VMAC[61],Andes45VPU[61] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 258 253.00 258 Andes45VMAC[253],Andes45VPU[253] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 26 21.00 26 Andes45VMAC[21],Andes45VPU[21] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 21.00 26 Andes45VMAC[21],Andes45VPU[21] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 26 21.00 26 Andes45VMAC[21],Andes45VPU[21] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 30 25.00 30 Andes45VMAC[25],Andes45VPU[25] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 38 33.00 38 Andes45VMAC[33],Andes45VPU[33] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 54 49.00 54 Andes45VMAC[49],Andes45VPU[49] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 17.00 22 Andes45VMAC[17],Andes45VPU[17] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 22 17.00 22 Andes45VMAC[17],Andes45VPU[17] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 26 21.00 26 Andes45VMAC[21],Andes45VPU[21] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 34 29.00 34 Andes45VMAC[29],Andes45VPU[29] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 50 45.00 50 Andes45VMAC[45],Andes45VPU[45] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 13.00 18 Andes45VMAC[13],Andes45VPU[13] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 22 17.00 22 Andes45VMAC[17],Andes45VPU[17] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 30 25.00 30 Andes45VMAC[25],Andes45VPU[25] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 46 41.00 46 Andes45VMAC[41],Andes45VPU[41] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 258 253.00 258 Andes45VMAC[253],Andes45VPU[253] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 514 509.00 514 Andes45VMAC[509],Andes45VPU[509] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1026 1021.00 1026 Andes45VMAC[1021],Andes45VPU[1021] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 66 61.00 66 Andes45VMAC[61],Andes45VPU[61] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 66 61.00 66 Andes45VMAC[61],Andes45VPU[61] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 130 125.00 130 Andes45VMAC[125],Andes45VPU[125] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 258 253.00 258 Andes45VMAC[253],Andes45VPU[253] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 514 509.00 514 Andes45VMAC[509],Andes45VPU[509] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 26 21.00 26 Andes45VMAC[21],Andes45VPU[21] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 21.00 26 Andes45VMAC[21],Andes45VPU[21] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 26 21.00 26 Andes45VMAC[21],Andes45VPU[21] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 34 29.00 34 Andes45VMAC[29],Andes45VPU[29] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 50 45.00 50 Andes45VMAC[45],Andes45VPU[45] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 82 77.00 82 Andes45VMAC[77],Andes45VPU[77] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 17.00 22 Andes45VMAC[17],Andes45VPU[17] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 22 17.00 22 Andes45VMAC[17],Andes45VPU[17] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 30 25.00 30 Andes45VMAC[25],Andes45VPU[25] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 46 41.00 46 Andes45VMAC[41],Andes45VPU[41] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 78 73.00 78 Andes45VMAC[73],Andes45VPU[73] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 294.00 - - - - - - 2384.00 - - 310.00 - 7584.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 11.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 13.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 17.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 11.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 15.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 7.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - - - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 11.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 13.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 17.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 11.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 15.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 7.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - - - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 11.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 13.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 17.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - - - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 253.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 509.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1021.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 61.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 61.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 253.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 509.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 29.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 61.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 253.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 21.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 21.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 21.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 25.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 33.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 49.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 17.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 17.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 21.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 29.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 45.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 13.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 17.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 25.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 41.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 253.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 509.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1021.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 61.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 61.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 125.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 253.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 509.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 21.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 21.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 21.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 29.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 45.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 77.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 17.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 17.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 25.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 41.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 73.00 - - vfwredusum.vs v8, v8, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s
new file mode 100644
index 0000000000000..2ce8d2261728a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vle-vse-vlm.s
@@ -0,0 +1,558 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vse8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vse16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vse32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vse64.v v8, (a0)
+
+# Unit-stride mask load/store
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vlm.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vsm.v v8, (a0)
+
+# Fault-only-first
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8ff.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16ff.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32ff.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 17 2.00 * 17 Andes45VLSU[2],Andes45VPU[2] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 17 4.00 * 17 Andes45VLSU[4],Andes45VPU[4] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 17 2.00 * 17 Andes45VLSU[2],Andes45VPU[2] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 17 4.00 * 17 Andes45VLSU[4],Andes45VPU[4] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 17 2.00 * 17 Andes45VLSU[2],Andes45VPU[2] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 17 4.00 * 17 Andes45VLSU[4],Andes45VPU[4] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 17 2.00 * 17 Andes45VLSU[2],Andes45VPU[2] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 17 4.00 * 17 Andes45VLSU[4],Andes45VPU[4] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 4.00 * 1 Andes45VLSU[4],Andes45VPU[4] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 4.00 * 1 Andes45VLSU[4],Andes45VPU[4] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 4.00 * 1 Andes45VLSU[4],Andes45VPU[4] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 4.00 * 1 Andes45VLSU[4],Andes45VPU[4] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 17 2.00 * 17 Andes45VLSU[2],Andes45VPU[2] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 17 4.00 * 17 Andes45VLSU[4],Andes45VPU[4] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 17 2.00 * 17 Andes45VLSU[2],Andes45VPU[2] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 17 4.00 * 17 Andes45VLSU[4],Andes45VPU[4] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 17 2.00 * 17 Andes45VLSU[2],Andes45VPU[2] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 17 4.00 * 17 Andes45VLSU[4],Andes45VPU[4] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 17 1.00 * 17 Andes45VLSU,Andes45VPU VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 17 2.00 * 17 Andes45VLSU[2],Andes45VPU[2] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 17 4.00 * 17 Andes45VLSU[4],Andes45VPU[4] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 17 8.00 * 17 Andes45VLSU[8],Andes45VPU[8] VLE64FF_V vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 80.00 - - - - - - - - - - 310.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s
new file mode 100644
index 0000000000000..64abe70a86e88
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlse-vsse.s
@@ -0,0 +1,332 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vlse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vlse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vlse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vlse64.v v8, (a0), t0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vsse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vsse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vsse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 81 8.00 * 81 Andes45VLSU[8],Andes45VPU[8] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 81 16.00 * 81 Andes45VLSU[16],Andes45VPU[16] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 81 32.00 * 81 Andes45VLSU[32],Andes45VPU[32] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 81 64.00 * 81 Andes45VLSU[64],Andes45VPU[64] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 81 128.00 * 81 Andes45VLSU[128],Andes45VPU[128] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 81 256.00 * 81 Andes45VLSU[256],Andes45VPU[256] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 81 512.00 * 81 Andes45VLSU[512],Andes45VPU[512] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 49 8.00 * 49 Andes45VLSU[8],Andes45VPU[8] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 49 16.00 * 49 Andes45VLSU[16],Andes45VPU[16] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 49 32.00 * 49 Andes45VLSU[32],Andes45VPU[32] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 49 64.00 * 49 Andes45VLSU[64],Andes45VPU[64] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 49 128.00 * 49 Andes45VLSU[128],Andes45VPU[128] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 49 256.00 * 49 Andes45VLSU[256],Andes45VPU[256] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 33 8.00 * 33 Andes45VLSU[8],Andes45VPU[8] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 33 16.00 * 33 Andes45VLSU[16],Andes45VPU[16] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 33 32.00 * 33 Andes45VLSU[32],Andes45VPU[32] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 33 64.00 * 33 Andes45VLSU[64],Andes45VPU[64] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 33 128.00 * 33 Andes45VLSU[128],Andes45VPU[128] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 25 8.00 * 25 Andes45VLSU[8],Andes45VPU[8] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 25 16.00 * 25 Andes45VLSU[16],Andes45VPU[16] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 25 32.00 * 25 Andes45VLSU[32],Andes45VPU[32] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 25 64.00 * 25 Andes45VLSU[64],Andes45VPU[64] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 128.00 * 1 Andes45VLSU[128],Andes45VPU[128] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 256.00 * 1 Andes45VLSU[256],Andes45VPU[256] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 512.00 * 1 Andes45VLSU[512],Andes45VPU[512] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 128.00 * 1 Andes45VLSU[128],Andes45VPU[128] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 256.00 * 1 Andes45VLSU[256],Andes45VPU[256] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 128.00 * 1 Andes45VLSU[128],Andes45VPU[128] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSE64_V vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 44.00 - - - - - - - - - - 3776.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 128.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 256.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 512.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 128.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 256.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 128.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 128.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 256.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 512.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 128.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 256.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 128.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s
new file mode 100644
index 0000000000000..3e30909ba6d47
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlseg-vsseg.s
@@ -0,0 +1,4743 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg6e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg7e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg7e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg7e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg8e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg8e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg8e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vsseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg6e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg6e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg6e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg7e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg7e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg7e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg7e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg7e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg8e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg8e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg8e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg8e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg8e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlsseg2e8.v v8, (a0), a1
+vsetvli zero, zero, e8, mf4, tu, mu
+vlsseg2e8.v v8, (a0), a1
+vsetvli zero, zero, e8, mf2, tu, mu
+vlsseg2e8.v v8, (a0), a1
+vsetvli zero, zero, e8, m1, tu, mu
+vlsseg2e8.v v8, (a0), a1
+vsetvli zero, zero, e8, m2, tu, mu
+vlsseg2e8.v v8, (a0), a1
+vsetvli zero, zero, e8, m4, tu, mu
+vlsseg2e8.v v8, (a0), a1
+vsetvli zero, zero, e16, mf4, tu, mu
+vlsseg2e16.v v8, (a0), a1
+vsetvli zero, zero, e16, mf2, tu, mu
+vlsseg2e16.v v8, (a0), a1
+vsetvli zero, zero, e16, m1, tu, mu
+vlsseg2e16.v v8, (a0), a1
+vsetvli zero, zero, e16, m2, tu, mu
+vlsseg2e16.v v8, (a0), a1
+vsetvli zero, zero, e16, m4, tu, mu
+vlsseg2e16.v v8, (a0), a1
+vsetvli zero, zero, e32, mf2, tu, mu
+vlsseg2e32.v v8, (a0), a1
+vsetvli zero, zero, e32, m1, tu, mu
+vlsseg2e32.v v8, (a0), a1
+vsetvli zero, zero, e32, m2, tu, mu
+vlsseg2e32.v v8, (a0), a1
+vsetvli zero, zero, e32, m4, tu, mu
+vlsseg2e32.v v8, (a0), a1
+vsetvli zero, zero, e64, m1, tu, mu
+vlsseg2e64.v v8, (a0), a1
+vsetvli zero, zero, e64, m2, tu, mu
+vlsseg2e64.v v8, (a0), a1
+vsetvli zero, zero, e64, m4, tu, mu
+vlsseg2e64.v v8, (a0), a1
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlsseg3e8.v v8, (a0), a1
+vsetvli zero, zero, e8, mf4, tu, mu
+vlsseg3e8.v v8, (a0), a1
+vsetvli zero, zero, e8, mf2, tu, mu
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+vloxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vloxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vloxseg8ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsuxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsuxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsuxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg2ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsuxseg2ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsuxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsuxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsuxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg3ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsuxseg3ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsuxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsuxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsuxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg4ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsuxseg4ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg5ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg5ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg5ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg6ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg7ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg8ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m4, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m4, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m4, tu, mu
+vsoxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg2ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg2ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m4, tu, mu
+vsoxseg2ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsoxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg3ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg3ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsoxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg4ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg4ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg5ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg5ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg5ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg6ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E64_V vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E64_V vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E64_V vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E64_V vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 4.00 * 1 Andes45VLSU[4],Andes45VPU[4] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 4.00 * 1 Andes45VLSU[4],Andes45VPU[4] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 4.00 * 1 Andes45VLSU[4],Andes45VPU[4] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 4.00 * 1 Andes45VLSU[4],Andes45VPU[4] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * 1 Andes45VLSU[2],Andes45VPU[2] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG5E64_V vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG6E64_V vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG7E64_V vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * 1 Andes45VLSU,Andes45VPU VSSEG8E64_V vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 82 128.00 * 82 Andes45VLSU[128],Andes45VPU[128] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 82 256.00 * 82 Andes45VLSU[256],Andes45VPU[256] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 50 64.00 * 50 Andes45VLSU[64],Andes45VPU[64] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 50 128.00 * 50 Andes45VLSU[128],Andes45VPU[128] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 34 32.00 * 34 Andes45VLSU[32],Andes45VPU[32] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 34 64.00 * 34 Andes45VLSU[64],Andes45VPU[64] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 26 16.00 * 26 Andes45VLSU[16],Andes45VPU[16] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 26 32.00 * 26 Andes45VLSU[32],Andes45VPU[32] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 82 128.00 * 82 Andes45VLSU[128],Andes45VPU[128] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 50 64.00 * 50 Andes45VLSU[64],Andes45VPU[64] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 34 32.00 * 34 Andes45VLSU[32],Andes45VPU[32] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 26 16.00 * 26 Andes45VLSU[16],Andes45VPU[16] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 82 128.00 * 82 Andes45VLSU[128],Andes45VPU[128] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 50 64.00 * 50 Andes45VLSU[64],Andes45VPU[64] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 34 32.00 * 34 Andes45VLSU[32],Andes45VPU[32] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 26 16.00 * 26 Andes45VLSU[16],Andes45VPU[16] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLSSEG5E64_V vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLSSEG6E64_V vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLSSEG7E64_V vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLSSEG8E64_V vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 128.00 * 1 Andes45VLSU[128],Andes45VPU[128] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 256.00 * 1 Andes45VLSU[256],Andes45VPU[256] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 128.00 * 1 Andes45VLSU[128],Andes45VPU[128] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 128.00 * 1 Andes45VLSU[128],Andes45VPU[128] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 128.00 * 1 Andes45VLSU[128],Andes45VPU[128] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG5E64_V vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG6E64_V vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG7E64_V vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSSSEG8E64_V vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 21 2.00 * 21 Andes45VLSU[2],Andes45VPU[2] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 3.00 * 22 Andes45VLSU[3],Andes45VPU[3] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 23 4.00 * 23 Andes45VLSU[4],Andes45VPU[4] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 5.00 * 24 Andes45VLSU[5],Andes45VPU[5] VLSEG5E64FF_V vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 25 6.00 * 25 Andes45VLSU[6],Andes45VPU[6] VLSEG6E64FF_V vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 7.00 * 26 Andes45VLSU[7],Andes45VPU[7] VLSEG7E64FF_V vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLSEG8E64FF_V vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 83 129.00 * 83 Andes45VLSU[129],Andes45VPU[129] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 83 259.00 * 83 Andes45VLSU[259],Andes45VPU[259] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 51 65.00 * 51 Andes45VLSU[65],Andes45VPU[65] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 51 131.00 * 51 Andes45VLSU[131],Andes45VPU[131] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 35 33.00 * 35 Andes45VLSU[33],Andes45VPU[33] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 35 67.00 * 35 Andes45VLSU[67],Andes45VPU[67] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 27 17.00 * 27 Andes45VLSU[17],Andes45VPU[17] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 27 35.00 * 27 Andes45VLSU[35],Andes45VPU[35] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 83 129.00 * 83 Andes45VLSU[129],Andes45VPU[129] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 51 65.00 * 51 Andes45VLSU[65],Andes45VPU[65] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 35 33.00 * 35 Andes45VLSU[33],Andes45VPU[33] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 27 17.00 * 27 Andes45VLSU[17],Andes45VPU[17] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 83 129.00 * 83 Andes45VLSU[129],Andes45VPU[129] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 51 65.00 * 51 Andes45VLSU[65],Andes45VPU[65] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 35 33.00 * 35 Andes45VLSU[33],Andes45VPU[33] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 27 17.00 * 27 Andes45VLSU[17],Andes45VPU[17] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLUXSEG5EI64_V vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLUXSEG6EI64_V vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLUXSEG7EI64_V vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLUXSEG8EI64_V vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 83 129.00 * 83 Andes45VLSU[129],Andes45VPU[129] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 83 259.00 * 83 Andes45VLSU[259],Andes45VPU[259] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 51 65.00 * 51 Andes45VLSU[65],Andes45VPU[65] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 51 131.00 * 51 Andes45VLSU[131],Andes45VPU[131] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 35 33.00 * 35 Andes45VLSU[33],Andes45VPU[33] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 35 67.00 * 35 Andes45VLSU[67],Andes45VPU[67] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 27 17.00 * 27 Andes45VLSU[17],Andes45VPU[17] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 27 35.00 * 27 Andes45VLSU[35],Andes45VPU[35] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 83 129.00 * 83 Andes45VLSU[129],Andes45VPU[129] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 51 65.00 * 51 Andes45VLSU[65],Andes45VPU[65] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 35 33.00 * 35 Andes45VLSU[33],Andes45VPU[33] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 27 17.00 * 27 Andes45VLSU[17],Andes45VPU[17] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 83 129.00 * 83 Andes45VLSU[129],Andes45VPU[129] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 51 65.00 * 51 Andes45VLSU[65],Andes45VPU[65] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 35 33.00 * 35 Andes45VLSU[33],Andes45VPU[33] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 27 17.00 * 27 Andes45VLSU[17],Andes45VPU[17] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLOXSEG5EI64_V vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLOXSEG6EI64_V vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLOXSEG7EI64_V vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 83 8.00 * 83 Andes45VLSU[8],Andes45VPU[8] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 83 16.00 * 83 Andes45VLSU[16],Andes45VPU[16] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 83 32.00 * 83 Andes45VLSU[32],Andes45VPU[32] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 83 64.00 * 83 Andes45VLSU[64],Andes45VPU[64] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 51 8.00 * 51 Andes45VLSU[8],Andes45VPU[8] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 51 16.00 * 51 Andes45VLSU[16],Andes45VPU[16] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 51 32.00 * 51 Andes45VLSU[32],Andes45VPU[32] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 8.00 * 35 Andes45VLSU[8],Andes45VPU[8] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 16.00 * 35 Andes45VLSU[16],Andes45VPU[16] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 27 8.00 * 27 Andes45VLSU[8],Andes45VPU[8] VLOXSEG8EI64_V vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 129.00 * 1 Andes45VLSU[129],Andes45VPU[129] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 65.00 * 1 Andes45VLSU[65],Andes45VPU[65] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 33.00 * 1 Andes45VLSU[33],Andes45VPU[33] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 17.00 * 1 Andes45VLSU[17],Andes45VPU[17] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 129.00 * 1 Andes45VLSU[129],Andes45VPU[129] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 65.00 * 1 Andes45VLSU[65],Andes45VPU[65] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 33.00 * 1 Andes45VLSU[33],Andes45VPU[33] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 17.00 * 1 Andes45VLSU[17],Andes45VPU[17] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 129.00 * 1 Andes45VLSU[129],Andes45VPU[129] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 65.00 * 1 Andes45VLSU[65],Andes45VPU[65] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 33.00 * 1 Andes45VLSU[33],Andes45VPU[33] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 17.00 * 1 Andes45VLSU[17],Andes45VPU[17] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG5EI64_V vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG6EI64_V vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG7EI64_V vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXSEG8EI64_V vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 129.00 * 1 Andes45VLSU[129],Andes45VPU[129] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 259.00 * 1 Andes45VLSU[259],Andes45VPU[259] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 65.00 * 1 Andes45VLSU[65],Andes45VPU[65] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 131.00 * 1 Andes45VLSU[131],Andes45VPU[131] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 33.00 * 1 Andes45VLSU[33],Andes45VPU[33] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 67.00 * 1 Andes45VLSU[67],Andes45VPU[67] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 17.00 * 1 Andes45VLSU[17],Andes45VPU[17] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 35.00 * 1 Andes45VLSU[35],Andes45VPU[35] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 129.00 * 1 Andes45VLSU[129],Andes45VPU[129] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 65.00 * 1 Andes45VLSU[65],Andes45VPU[65] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 33.00 * 1 Andes45VLSU[33],Andes45VPU[33] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 17.00 * 1 Andes45VLSU[17],Andes45VPU[17] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 129.00 * 1 Andes45VLSU[129],Andes45VPU[129] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 65.00 * 1 Andes45VLSU[65],Andes45VPU[65] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 33.00 * 1 Andes45VLSU[33],Andes45VPU[33] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 17.00 * 1 Andes45VLSU[17],Andes45VPU[17] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG5EI64_V vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG6EI64_V vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG7EI64_V vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXSEG8EI64_V vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 770.00 - - - - - - - - - - 16558.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - - - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 6.00 - - - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 6.00 - - - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 6.00 - - - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 - - - vlseg3e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 6.00 - - - vlseg3e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlseg4e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - - - vlseg4e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vlseg4e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e16.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e32.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - - - vlseg5e64.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 6.00 - - - vlseg6e8.v v8, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 35.00 - - - vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 129.00 - - - vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 65.00 - - - vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 33.00 - - - vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 17.00 - - - vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 129.00 - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 65.00 - - - vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 33.00 - - - vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 17.00 - - - vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s
new file mode 100644
index 0000000000000..ee955ec4559fc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-vlxe-vsxe.s
@@ -0,0 +1,604 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vluxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vluxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vluxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vluxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vloxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vloxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vloxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vloxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsuxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsuxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsuxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsuxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsoxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsoxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsoxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Andes45ALU:2
+# CHECK-NEXT: [1] - Andes45CSR:1
+# CHECK-NEXT: [2] - Andes45FDIV:1
+# CHECK-NEXT: [3] - Andes45FMAC:1
+# CHECK-NEXT: [4] - Andes45FMISC:1
+# CHECK-NEXT: [5] - Andes45FMV:1
+# CHECK-NEXT: [6] - Andes45LSU:1
+# CHECK-NEXT: [7] - Andes45MDU:1
+# CHECK-NEXT: [8] - Andes45VALU:1
+# CHECK-NEXT: [9] - Andes45VDIV:1
+# CHECK-NEXT: [10] - Andes45VFDIV:1
+# CHECK-NEXT: [11] - Andes45VFMIS:1
+# CHECK-NEXT: [12] - Andes45VLSU:1
+# CHECK-NEXT: [13] - Andes45VMAC:1
+# CHECK-NEXT: [14] - Andes45VMASK:1
+# CHECK-NEXT: [15] - Andes45VPERMUT:1
+# CHECK-NEXT: [16] - Andes45VPU:8 Andes45VALU, Andes45VMAC, Andes45VFMIS, Andes45VPERMUT, Andes45VDIV, Andes45VFDIV, Andes45VMASK, Andes45VLSU
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 82 129.00 * 82 Andes45VLSU[129],Andes45VPU[129] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 82 259.00 * 82 Andes45VLSU[259],Andes45VPU[259] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 82 519.00 * 82 Andes45VLSU[519],Andes45VPU[519] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 50 65.00 * 50 Andes45VLSU[65],Andes45VPU[65] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 50 131.00 * 50 Andes45VLSU[131],Andes45VPU[131] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 50 263.00 * 50 Andes45VLSU[263],Andes45VPU[263] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 34 33.00 * 34 Andes45VLSU[33],Andes45VPU[33] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 34 67.00 * 34 Andes45VLSU[67],Andes45VPU[67] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 34 135.00 * 34 Andes45VLSU[135],Andes45VPU[135] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 26 17.00 * 26 Andes45VLSU[17],Andes45VPU[17] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 26 35.00 * 26 Andes45VLSU[35],Andes45VPU[35] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 26 71.00 * 26 Andes45VLSU[71],Andes45VPU[71] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 82 8.00 * 82 Andes45VLSU[8],Andes45VPU[8] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 82 16.00 * 82 Andes45VLSU[16],Andes45VPU[16] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 82 32.00 * 82 Andes45VLSU[32],Andes45VPU[32] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 82 64.00 * 82 Andes45VLSU[64],Andes45VPU[64] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 82 129.00 * 82 Andes45VLSU[129],Andes45VPU[129] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 82 259.00 * 82 Andes45VLSU[259],Andes45VPU[259] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 82 519.00 * 82 Andes45VLSU[519],Andes45VPU[519] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 50 8.00 * 50 Andes45VLSU[8],Andes45VPU[8] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 50 16.00 * 50 Andes45VLSU[16],Andes45VPU[16] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 50 32.00 * 50 Andes45VLSU[32],Andes45VPU[32] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 50 65.00 * 50 Andes45VLSU[65],Andes45VPU[65] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 50 131.00 * 50 Andes45VLSU[131],Andes45VPU[131] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 50 263.00 * 50 Andes45VLSU[263],Andes45VPU[263] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 34 8.00 * 34 Andes45VLSU[8],Andes45VPU[8] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 34 16.00 * 34 Andes45VLSU[16],Andes45VPU[16] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 34 33.00 * 34 Andes45VLSU[33],Andes45VPU[33] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 34 67.00 * 34 Andes45VLSU[67],Andes45VPU[67] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 34 135.00 * 34 Andes45VLSU[135],Andes45VPU[135] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 26 8.00 * 26 Andes45VLSU[8],Andes45VPU[8] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 26 17.00 * 26 Andes45VLSU[17],Andes45VPU[17] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 26 35.00 * 26 Andes45VLSU[35],Andes45VPU[35] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 26 71.00 * 26 Andes45VLSU[71],Andes45VPU[71] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 129.00 * 1 Andes45VLSU[129],Andes45VPU[129] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 259.00 * 1 Andes45VLSU[259],Andes45VPU[259] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 519.00 * 1 Andes45VLSU[519],Andes45VPU[519] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 65.00 * 1 Andes45VLSU[65],Andes45VPU[65] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 131.00 * 1 Andes45VLSU[131],Andes45VPU[131] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 263.00 * 1 Andes45VLSU[263],Andes45VPU[263] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 33.00 * 1 Andes45VLSU[33],Andes45VPU[33] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 67.00 * 1 Andes45VLSU[67],Andes45VPU[67] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 135.00 * 1 Andes45VLSU[135],Andes45VPU[135] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 17.00 * 1 Andes45VLSU[17],Andes45VPU[17] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 35.00 * 1 Andes45VLSU[35],Andes45VPU[35] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 71.00 * 1 Andes45VLSU[71],Andes45VPU[71] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 64.00 * 1 Andes45VLSU[64],Andes45VPU[64] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 129.00 * 1 Andes45VLSU[129],Andes45VPU[129] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 259.00 * 1 Andes45VLSU[259],Andes45VPU[259] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 519.00 * 1 Andes45VLSU[519],Andes45VPU[519] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 32.00 * 1 Andes45VLSU[32],Andes45VPU[32] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 65.00 * 1 Andes45VLSU[65],Andes45VPU[65] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 131.00 * 1 Andes45VLSU[131],Andes45VPU[131] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 263.00 * 1 Andes45VLSU[263],Andes45VPU[263] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 16.00 * 1 Andes45VLSU[16],Andes45VPU[16] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 33.00 * 1 Andes45VLSU[33],Andes45VPU[33] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 67.00 * 1 Andes45VLSU[67],Andes45VPU[67] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 135.00 * 1 Andes45VLSU[135],Andes45VPU[135] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 8.00 * 1 Andes45VLSU[8],Andes45VPU[8] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 17.00 * 1 Andes45VLSU[17],Andes45VPU[17] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 35.00 * 1 Andes45VLSU[35],Andes45VPU[35] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 71.00 * 1 Andes45VLSU[71],Andes45VPU[71] VSOXEI64_V vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Andes45ALU
+# CHECK-NEXT: [0.1] - Andes45ALU
+# CHECK-NEXT: [1] - Andes45CSR
+# CHECK-NEXT: [2] - Andes45FDIV
+# CHECK-NEXT: [3] - Andes45FMAC
+# CHECK-NEXT: [4] - Andes45FMISC
+# CHECK-NEXT: [5] - Andes45FMV
+# CHECK-NEXT: [6] - Andes45LSU
+# CHECK-NEXT: [7] - Andes45MDU
+# CHECK-NEXT: [8] - Andes45VALU
+# CHECK-NEXT: [9] - Andes45VDIV
+# CHECK-NEXT: [10] - Andes45VFDIV
+# CHECK-NEXT: [11] - Andes45VFMIS
+# CHECK-NEXT: [12] - Andes45VLSU
+# CHECK-NEXT: [13] - Andes45VMAC
+# CHECK-NEXT: [14] - Andes45VMASK
+# CHECK-NEXT: [15] - Andes45VPERMUT
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
+# CHECK-NEXT: - - 88.00 - - - - - - - - - - 7728.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 129.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 259.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 519.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 65.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 131.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 263.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 33.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 67.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 135.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 17.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 35.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 71.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 129.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 259.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 519.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 65.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 131.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 263.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 33.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 67.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 135.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 17.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 35.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 71.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 64.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 129.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 259.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 519.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 8.00 - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 16.00 - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 32.00 - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 65.00 - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - 131.00 - - - vsuxei16.v v8, (a0), v0
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>From 37bbd732ccd36c85c55d1f99f0666c4505f39e03 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Mon, 17 Nov 2025 08:43:57 +0800
Subject: [PATCH 2/2] Remove unusable comment
---
llvm/lib/Target/RISCV/RISCVSchedAndes45.td | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index 207a240e5c896..d709a640874f5 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -8,7 +8,6 @@
//===----------------------------------------------------------------------===//
-// Refer to `Table 5: Supported VLEN and DLEN` for legal VLEN and DLEN.
defvar Andes45VLEN = 512;
defvar Andes45DLEN = 512;
defvar Andes45VLEN_DLEN_RATIO = !div(Andes45VLEN, Andes45DLEN);
@@ -16,7 +15,6 @@ defvar Andes45VLEN_DLEN_RATIO = !div(Andes45VLEN, Andes45DLEN);
assert !or(!eq(Andes45VLEN_DLEN_RATIO, 1), !eq(Andes45VLEN_DLEN_RATIO, 2)),
"Andes45VLEN / Andes45DLEN should be 1 or 2";
-// Refer to `Table 6: Supported DLEN and BIU_DATA_WIDTH` for legal BIU_DATA_WIDTH.
defvar Andes45BIU_DATA_WIDTH = 512;
defvar Andes45DLEN_BIU_DATA_WIDTH_RATIO = !div(Andes45DLEN, Andes45BIU_DATA_WIDTH);
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