[llvm] [RISCV] Implement RVV scheduling model for andes 45 series processor. (PR #167821)

[Jim Lin via llvm-commits]

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@@ -8,7 +8,238 @@
 
 //===----------------------------------------------------------------------===//
 
-// FIXME: Implement sheduling model for V and other extensions.
+// Refer to `Table 5: Supported VLEN and DLEN` for legal VLEN and DLEN.
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tclin914 wrote:

That is our internal document which describes the latency and throughput of instructions. If you mind the unusable comment here, I can remove it.

https://github.com/llvm/llvm-project/pull/167821