[llvm] [DAG] MatchLoadCombine - match swapped loads (PR #167416)

[Simon Pilgrim via llvm-commits]

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@@ -9772,12 +9772,40 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
                           MemVT))
     return SDValue();
 
+  auto IsRotateLoaded = [](ArrayRef<int64_t> ByteOffsets, int64_t FirstOffset,
+                           unsigned BitWidth) {
+    // Ensure that we have the correct width type, we want to combine two 32
+    // loads into a 64 bit load.
+    if (BitWidth != 64 || ByteOffsets.size() != 8)
+      return false;
+
+    constexpr unsigned FourBytes = 4;
+
+    for (unsigned i = 0; i < FourBytes; ++i) {
+      // Check the lower 4 bytes come from the higher memory address.
+      if (ByteOffsets[i] != FirstOffset + i + FourBytes)
+        return false;
+      // Check the higher 4 bytes come from the lower memory adderess.
+      if (ByteOffsets[i + FourBytes] != FirstOffset + i)
+        return false;
+    }
+    return true;
+  };
+
   // Check if the bytes of the OR we are looking at match with either big or
   // little endian value load
   std::optional<bool> IsBigEndian = isBigEndian(
       ArrayRef(ByteOffsets).drop_back(ZeroExtendedBytes), FirstOffset);
-  if (!IsBigEndian)
-    return SDValue();
+
+  bool IsRotated = false;
----------------
RKSimon wrote:

Pull this out like isBigEndian, something like:
```
static std::optional<unsigned> isRotated(ArrayRef<int64_t> ByteOffsets, int64_t FirstOffset)
```
returning the rotation bit amount on success

https://github.com/llvm/llvm-project/pull/167416