[llvm] [DAG] MatchLoadCombine - match swapped loads (PR #167416)

[Simon Pilgrim via llvm-commits]

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@@ -9772,12 +9772,40 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
                           MemVT))
     return SDValue();
 
+  auto IsRotateLoaded = [](ArrayRef<int64_t> ByteOffsets, int64_t FirstOffset,
+                           unsigned BitWidth) {
+    // Ensure that we have the correct width type, we want to combine two 32
+    // loads into a 64 bit load.
+    if (BitWidth != 64 || ByteOffsets.size() != 8)
+      return false;
+
+    constexpr unsigned FourBytes = 4;
+
+    for (unsigned i = 0; i < FourBytes; ++i) {
+      // Check the lower 4 bytes come from the higher memory address.
+      if (ByteOffsets[i] != FirstOffset + i + FourBytes)
+        return false;
+      // Check the higher 4 bytes come from the lower memory adderess.
+      if (ByteOffsets[i + FourBytes] != FirstOffset + i)
+        return false;
+    }
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RKSimon wrote:

This is very limiting - I was expecting something that was a bit more generic - we're after a pattern match that returns a common rotation amount from a sequential series of load offsets

https://github.com/llvm/llvm-project/pull/167416