[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Martin Storsjö via llvm-commits]

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@@ -1568,8 +1569,14 @@ static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
     return true;
   if (!NeedsWinCFI)
     return false;
+  // ARM64EC introduced `save_any_regp` which expects 16-byte alignment.
+  // Accomodate that by ensuring that we re-align to 16-bytes when doing paired
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mstorsjo wrote:

> > Also do note that if we rearrange the way we lay out the stores, we can end up matching the patterns for packed unwind info much less often
> This only applies to cases where we can use packed unwind in the first place... which obviously isn't relevant if we're spilling registers less than x19.

Yes, clearly. My point was that if we rearrange the stores of registers >= x19 e.g. so that they are paired in a different fashion, even if it results in the same number of instructions, it would still cause mismatches with the packed format. So if we want to keep the efficient packed encoding, we really need to keep the existing layout and pairing/code generation for those registers.

https://github.com/llvm/llvm-project/pull/166902