[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Eli Friedman via llvm-commits]

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@@ -1568,8 +1569,14 @@ static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
     return true;
   if (!NeedsWinCFI)
     return false;
+  // ARM64EC introduced `save_any_regp` which expects 16-byte alignment.
+  // Accomodate that by ensuring that we re-align to 16-bytes when doing paired
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efriedma-quic wrote:

> Also do note that if we rearrange the way we lay out the stores, we can end up matching the patterns for packed unwind info much less often

This only applies to cases where we can use packed unwind in the first place... which obviously isn't relevant if we're spilling registers less than x19.

> Hmm, do you have a pointer as to where we could adjust that alignment?

AArch64FrameLowering::determineCalleeSaves and computeCalleeSaveRegisterPairs work together to lay out the callee saves.

But I'm fine with just doing the simple thing for registers less the x19 for the initial fix, then we can refine it later.

https://github.com/llvm/llvm-project/pull/166902