[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Saleem Abdulrasool via llvm-commits]

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@@ -1568,8 +1569,14 @@ static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
     return true;
   if (!NeedsWinCFI)
     return false;
+  // ARM64EC introduced `save_any_regp` which expects 16-byte alignment.
+  // Accomodate that by ensuring that we re-align to 16-bytes when doing paired
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compnerd wrote:

@mstorsjo yeah, we definitely do want the benefits of the pdata representation whenever possible rather than spilling into xdata. I'm not entirely sure I see a good way to determine that though. I suppose that a first approximation would be to special case registers < r19.

https://github.com/llvm/llvm-project/pull/166902