[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Saleem Abdulrasool via llvm-commits]

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@@ -1568,8 +1569,14 @@ static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
     return true;
   if (!NeedsWinCFI)
     return false;
+  // ARM64EC introduced `save_any_regp` which expects 16-byte alignment.
+  // Accomodate that by ensuring that we re-align to 16-bytes when doing paired
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compnerd wrote:

Hmm, do you have a pointer as to where we could adjust that alignment? It seems that this is less about pairing and more about the spill slot handling?

https://github.com/llvm/llvm-project/pull/166902