[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Benjamin Maxwell via llvm-commits]

================
@@ -1568,8 +1569,14 @@ static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
     return true;
   if (!NeedsWinCFI)
     return false;
+  // ARM64EC introduced `save_any_regp` which expects 16-byte alignment.
+  // Accomodate that by ensuring that we re-align to 16-bytes when doing paired
+  // spills. Carve out an exception for {FP,LR} pairs which we perform without
+  // 16-byte alignment.
----------------
MacDue wrote:

IIUC, this is:
```suggestion
  // ARM64EC introduced `save_any_regp`, which expects 16-byte alignment.
  // This is handled by only allowing paired spills for registers spilled at
  // even positions (which should be 16-byte aligned, as other GPRs/FPRs are
  // 8-bytes). We carve out an exception for {FP,LR}, which does not require
  // 16-byte alignment.
```


https://github.com/llvm/llvm-project/pull/166902