[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Saleem Abdulrasool via llvm-commits]

================
@@ -1752,15 +1760,15 @@ void computeCalleeSaveRegisterPairs(const AArch64FrameLowering &AFL,
       switch (RPI.Type) {
       case RegPairInfo::GPR:
         if (AArch64::GPR64RegClass.contains(NextReg) &&
-            !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows,
-                                       NeedsWinCFI, NeedsFrameRecord, IsFirst,
-                                       TRI))
+            !invalidateRegisterPairing(i - FirstReg, RPI.Reg1, NextReg,
----------------
compnerd wrote:

Sure, I can rename it to `SpillCount`.

https://github.com/llvm/llvm-project/pull/166902